mtd: spi-nor: gigadevice: Disable 16bit SR operation for gd25lx256e flash

Amit Kumar Mahapatra · michalsimek · commit 1c6af1076f3b · 2024-04-27T07:11:16.000+02:00
Gigadevice gd25lx256e flash doesn't support 16bit Status Register(SR) read/write operations, but during flash lock/unlock spi-nor issues 16Bit SR operations that results in flash protection failure. Disable 16bit SR read/write for gd25lx256e in spi-nor fixups. Fixes: 9cc5feb ("mtd: spi-nor: gigadevice: Add support for GD25LX256E") Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
@@ -110,6 +110,7 @@ static void gd25lx256e_default_init(struct spi_nor *nor)
 {
 	struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
 
+	nor->flags &= ~SNOR_F_HAS_16BIT_SR;
 	params->set_octal_dtr = spi_nor_gigadevice_octal_dtr_enable;
 	params->set_4byte_addr_mode = gd25lx256e_set_4byte_addr_mode;
 }

Original file line number	Diff line number	Diff line change
`@@ -110,6 +110,7 @@ static void gd25lx256e_default_init(struct spi_nor *nor)`
`110`	`110`	`{`
`111`	`111`	`struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);`
`112`	`112`
	`113`	`+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;`
`113`	`114`	`params->set_octal_dtr = spi_nor_gigadevice_octal_dtr_enable;`
`114`	`115`	`params->set_4byte_addr_mode = gd25lx256e_set_4byte_addr_mode;`
`115`	`116`	`}`