projects:ad9081_fmca_ebz_x_band: Fix synchronization #1823
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When the data offload souruce and destination clock are connected to the same source there is a DRC error. By exposing the ASYNC_CLK parameter and setting it to 0 in this use-case the issue is solved. Signed-off-by: PopPaul2021 <paul.pop@analog.com>
Signed-off-by: PopPaul2021 <paul.pop@analog.com>
The CDC was moved from the DO to the DMA. The DMA clock was moved from the 250MHz PS clock to a 330MHz clock generated by the clock wizard. The cache coherency was disabled in order to have the HP ports working at maximum frequency. Signed-off-by: PopPaul2021 <paul.pop@analog.com>
The block diagram of the HDL design was updated. Notes regarding the system's use-case were added. Signed-off-by: PopPaul2021 <paul.pop@analog.com>
PopPaul2021
requested review from
IuliaCMoldovan,
gastmaier,
StancaPop,
LBFFilho,
podgori,
bluncan,
acostina,
AndreiGrozav and
sarpadi
as code owners
The false path has to be set only when in async_clk mode. Signed-off-by: PopPaul2021 <paul.pop@analog.com>
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PR Description
The CDC was moved from the DO to the DMA.
The DMA clock was moved from the 250MHz PS clock to a 330MHz clock generated by the clock wizard.
The cache coherency was disabled in order to have the HP ports working at maximum frequency.
PR Type
PR Checklist