Lattice support for ad738x_fmc project on LFCPNX-EVN (lfcpnx) carrier board.

docs/user_guide/build_hdl.rst

@@ -849,14 +849,18 @@ The **sof** file is used to program the device.
 
 The Lattice build is in a very early version. We are just adding the first
 version of library infrastructure support.
-Currently, we only have a single early-version base design that builds almost
-like the other ones. For Lattice, there are separate tools for creating
-a block design **(Propel Builder)** and building an HDL design **(Radiant)**.
+
+.. note::
+
+   Currently, we have only one supported project --- the **ad738x_fmc** for
+   **LFCPNX-EVN** carrier board, in ``hdl/projects/ad738x_fmc/lfcpnx`` folder.
+   For Lattice, there are separate tools for creating
+   a block design **(Propel Builder)** and building an HDL design **(Radiant)**.
 
 To build a project, go to the carrier folder and run ``make``. For now, you can
-try to build the only base design we have available for
-**CertusPro-NX Evaluation Board** by entering the base design directory and
-running ``make``.
+try to build the **ad738x_fmc** project that we have available for
+**CertusPro-NX Evaluation Board** by entering the
+``hdl/projects/ad738x_fmc/lfcpnx`` directory and running ``make``.
 
 .. shell:: bash
 

library/interfaces_ltt/Makefile

@@ -25,13 +25,16 @@ LTT_INTERFACES += analog.com/ADI/spi_engine_offload_ctrl/1.0/spi_engine_offload_
 LTT_INTERFACES += analog.com/ADI/spi_engine_offload_ctrl/1.0/spi_engine_offload_ctrl_rtl.xml
 LTT_INTERFACES += analog.com/ADI/if_framelock/1.0/if_framelock.xml
 LTT_INTERFACES += analog.com/ADI/if_framelock/1.0/if_framelock_rtl.xml
+LTT_INTERFACES += analog.com/ADI/spi_engine_interconnect_ctrl/1.0/spi_engine_interconnect_ctrl.xml
+LTT_INTERFACES += analog.com/ADI/spi_engine_interconnect_ctrl/1.0/spi_engine_interconnect_ctrl_rtl.xml
 
 CLEAN_TARGETS += analog.com/ADI/fifo_rd
 CLEAN_TARGETS += analog.com/ADI/fifo_wr
 CLEAN_TARGETS += analog.com/ADI/spi_master
 CLEAN_TARGETS += analog.com/ADI/spi_engine_ctrl
 CLEAN_TARGETS += analog.com/ADI/spi_engine_offload_ctrl
 CLEAN_TARGETS += analog.com/ADI/if_framelock
+CLEAN_TARGETS += analog.com/ADI/spi_engine_interconnect_ctrl
 
 ifeq ($(LATTICE_DEFAULT_PATHS),1)
 LTT_INTERFACES := $(LTT_INTERFACES) $(foreach dep,$(LTT_INTERFACES),$(LATTICE_DEFAULT_INTERFACE_PATH)/$(dep))

library/interfaces_ltt/interfaces_ltt.tcl

@@ -74,6 +74,16 @@ set if [ipl::create_interface \
     }]
 ipl::generate_interface $if
 
+set if [ipl::create_interface \
+    -vlnv {analog.com:ADI:spi_engine_interconnect_ctrl:1.0} \
+    -directConnection true \
+    -isAddressable false \
+    -description "ADI SPI Engine Interconnect Control Interface" \
+    -ports {
+        {-n INTERCONNECT_DIR -p required -w 1 -d out}
+    }]
+ipl::generate_interface $if
+
 set if [ipl::create_interface \
     -vlnv {analog.com:ADI:spi_master:1.0} \
     -directConnection true \

library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ltt.tcl

@@ -67,6 +67,16 @@ foreach prefix [list "s0" "s1"] {
         -vlnv {analog.com:ADI:spi_engine_ctrl:1.0}]
 }
 
+set ip [ipl::add_interface -ip $ip \
+    -inst_name s_interconnect_ctrl \
+    -display_name s_interconnect_ctrl \
+    -description spi_engine_interconnect_ctrl \
+    -master_slave slave \
+    -portmap { \
+        {"interconnect_dir" "INTERCONNECT_DIR"} \
+    } \
+    -vlnv {analog.com:ADI:spi_engine_interconnect_ctrl:1.0}]
+
 set ip [ipl::add_ip_files -ip $ip -dpath rtl -flist [list \
     "spi_engine_interconnect.v" ]]
 

library/spi_engine/spi_engine_offload/spi_engine_offload_ltt.tcl

@@ -62,6 +62,16 @@ set ip [ipl::add_interface -ip $ip \
     } \
     -vlnv {analog.com:ADI:spi_engine_ctrl:1.0}]
 
+set ip [ipl::add_interface -ip $ip \
+    -inst_name m_interconnect_ctrl \
+    -display_name m_interconnect_ctrl \
+    -description spi_engine_interconnect_ctrl \
+    -master_slave master \
+    -portmap { \
+        {"interconnect_dir" "INTERCONNECT_DIR"} \
+    } \
+    -vlnv {analog.com:ADI:spi_engine_interconnect_ctrl:1.0}]
+
 set ip [ipl::add_interface -ip $ip \
     -inst_name offload_sdi \
     -display_name offload_sdi \

projects/ad738x_fmc/common/ad738x_pb.tcl

@@ -0,0 +1,166 @@
+###############################################################################
+## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+########### This file contains only the tcl commands for importing lib ########
+########### components and the assembly of the design. ########################
+
+## configure ip components and add to design. #################################
+# set dir [pwd]
+# cd $ad_hdl_dir/library/axi_dmac
+# source ./axi_dmac_ltt.tcl
+# cd $ad_hdl_dir/library/axi_pwm_gen
+# source ./axi_pwm_gen_ltt.tcl
+# cd $ad_hdl_dir/library/spi_engine/axi_spi_engine
+# source ./axi_spi_engine_ltt.tcl
+# cd $ad_hdl_dir/library/spi_engine/spi_engine_offload
+# source ./spi_engine_offload_ltt.tcl
+# cd $ad_hdl_dir/library/spi_engine/spi_engine_interconnect
+# source ./spi_engine_interconnect_ltt.tcl
+# cd $ad_hdl_dir/library/spi_engine/spi_engine_execution
+# source ./spi_engine_execution_ltt.tcl
+# cd $dir
+
+adi_ip_update $project_name -vlnv {latticesemi.com:ip:axi_interc0:2.0.1} \
+  -meta_vlnv {latticesemi.com:ip:axi_interconnect:2.0.1} \
+  -cfg_value {
+    EXT_MAS_AXI_ID_WIDTH:1,
+    EXT_SLV_AXI_ID_WIDTH:8,
+    TOTAL_EXTMAS_CNT:2,
+    TOTAL_EXTSLV_CNT:5,
+    ext_slv_axi_protocol_2:1,
+    ext_slv_axi_protocol_3:1,
+    ext_slv_axi_protocol_4:1
+  } \
+  -ip_iname "axi_interc0_inst"
+adi_ip_instance -vlnv {analog.com:ip:axi_spi0:1.0} \
+  -meta_vlnv {analog.com:ip:axi_spi_engine:1.0} \
+  -cfg_value {
+    ASYNC_SPI_CLK:0,
+    DATA_WIDTH:16,
+    MM_IF_TYPE:0,
+    NUM_OFFLOAD:1,
+    NUM_OF_SDI:4
+  } \
+  -ip_iname "axi_spi0_inst"
+adi_ip_instance -vlnv {analog.com:ip:pwm0:1.0} \
+  -meta_vlnv {analog.com:ip:axi_pwm_gen:1.0} \
+  -cfg_value {
+    ASYNC_CLK_EN:0,
+    PULSE_0_PERIOD:120,
+    PULSE_0_WIDTH:10
+  } \
+  -ip_iname "pwm0_inst"
+adi_ip_instance -vlnv {analog.com:ip:spi_offload0:1.0} \
+  -meta_vlnv {analog.com:ip:spi_engine_offload:1.0} \
+  -cfg_value {
+    ASYNC_SPI_CLK:0,
+    DATA_WIDTH:16,
+    NUM_OF_SDI:4
+  } \
+  -ip_iname "spi_offload0_inst"
+adi_ip_instance -vlnv {analog.com:ip:dmac0:1.0} \
+  -meta_vlnv {analog.com:ip:axi_dmac:1.0} \
+  -cfg_value {
+    ASYNC_CLK_DEST_REQ:0,
+    ASYNC_CLK_DEST_SG:0,
+    ASYNC_CLK_REQ_SG:0,
+    ASYNC_CLK_REQ_SRC:0,
+    ASYNC_CLK_SRC_DEST:0,
+    ASYNC_CLK_SRC_SG:0,
+    AXI_SLICE_DEST:1,
+    AXI_SLICE_SRC:0,
+    DMA_DATA_WIDTH_DEST:32,
+    DMA_DATA_WIDTH_SRC:64,
+    DMA_TYPE_DEST:0,
+    DMA_TYPE_SRC:1
+  } \
+  -ip_iname "dmac0_inst"
+adi_ip_instance -vlnv {analog.com:ip:spi_interc0:1.0} \
+  -meta_vlnv {analog.com:ip:spi_engine_interconnect:1.0} \
+  -cfg_value {DATA_WIDTH:16,NUM_OF_SDI:4} \
+  -ip_iname "spi_interc0_inst"
+adi_ip_instance -vlnv {analog.com:ip:spi_exec0:1.0} \
+  -meta_vlnv {analog.com:ip:spi_engine_execution:1.0} \
+  -cfg_value {
+    DATA_WIDTH:16,
+    NUM_OF_SDI:4,
+    SDI_DELAY:1
+  } \
+  -ip_iname "spi_exec0_inst"
+adi_ip_instance -vlnv {latticesemi.com:ip:sysmem_dmac0:2.3.0} \
+  -meta_vlnv {latticesemi.com:ip:system_memory:2.3.0} \
+  -cfg_value {
+    ADDR_DEPTH:8192,
+    INTERFACE:AXI4,
+    MEMORY_TYPE:LRAM
+  } \
+  -ip_iname "sysmem_dmac0_inst"
+
+sbp_connect_net -name [sbp_get_nets -from $project_name/pll0_inst *clkop*] \
+  "$project_name/pwm0_inst/s_axi_aclk" \
+  "$project_name/axi_spi0_inst/s_axi_aclk" \
+  "$project_name/axi_spi0_inst/spi_clk" \
+  "$project_name/spi_offload0_inst/spi_clk" \
+  "$project_name/spi_offload0_inst/ctrl_clk" \
+  "$project_name/dmac0_inst/s_axi_aclk" \
+  "$project_name/dmac0_inst/s_axis_aclk" \
+  "$project_name/dmac0_inst/m_dest_axi_aclk" \
+  "$project_name/spi_interc0_inst/clk" \
+  "$project_name/spi_exec0_inst/clk" \
+  "$project_name/sysmem_dmac0_inst/axi_aclk_i"
+
+sbp_connect_net -name [sbp_get_nets -from $project_name/cpu0_inst *resetn*] \
+  "$project_name/pwm0_inst/s_axi_aresetn" \
+  "$project_name/axi_spi0_inst/s_axi_aresetn" \
+  "$project_name/dmac0_inst/s_axi_aresetn" \
+  "$project_name/dmac0_inst/m_dest_axi_aresetn" \
+  "$project_name/sysmem_dmac0_inst/axi_resetn_i"
+
+sbp_connect_net "$project_name/axi_spi0_inst/spi_resetn" \
+  "$project_name/spi_offload0_inst/spi_resetn" \
+  "$project_name/spi_interc0_inst/resetn" \
+  "$project_name/spi_exec0_inst/resetn"
+
+sbp_connect_interface_net "$project_name/axi_spi0_inst/IRQ" \
+  "$project_name/cpu0_inst/IRQ_S7"
+sbp_connect_interface_net "$project_name/dmac0_inst/IRQ" \
+  "$project_name/cpu0_inst/IRQ_S6"
+
+sbp_connect_interface_net $project_name/spi_offload0_inst/spi_engine_offload_ctrl \
+  $project_name/axi_spi0_inst/spi_engine_offload_ctrl0
+sbp_connect_interface_net $project_name/dmac0_inst/s_axis \
+  $project_name/spi_offload0_inst/offload_sdi
+sbp_connect_interface_net $project_name/spi_interc0_inst/s0_ctrl \
+  $project_name/spi_offload0_inst/spi_engine_ctrl
+sbp_connect_interface_net $project_name/spi_interc0_inst/s1_ctrl \
+  $project_name/axi_spi0_inst/spi_engine_ctrl
+sbp_connect_interface_net $project_name/spi_exec0_inst/spi_engine_ctrl \
+  $project_name/spi_interc0_inst/m_ctrl
+sbp_connect_interface_net $project_name/axi_interc0_inst/AXIL_M04 \
+  $project_name/pwm0_inst/s_axi
+sbp_connect_interface_net $project_name/axi_interc0_inst/AXIL_M03 \
+  $project_name/axi_spi0_inst/s_axi
+sbp_connect_interface_net $project_name/axi_interc0_inst/AXI_S01 \
+  $project_name/dmac0_inst/m_dest_axi
+sbp_connect_net $project_name/spi_offload0_inst/trigger \
+  $project_name/pwm0_inst/pwm_0
+sbp_connect_interface_net $project_name/dmac0_inst/s_axi \
+  $project_name/axi_interc0_inst/AXIL_M02
+sbp_connect_interface_net $project_name/axi_interc0_inst/AXI_M01 \
+  $project_name/sysmem_dmac0_inst/AXI_S0
+sbp_connect_interface_net $project_name/spi_offload0_inst/m_interconnect_ctrl \
+  $project_name/spi_interc0_inst/s_interconnect_ctrl
+
+sbp_export_interfaces $project_name/spi_exec0_inst/spi_master
+sbp_rename -name  {spi_master0} $project_name/spi_exec0_inst_spi_master_interface
+
+sbp_assign_addr_seg -offset 'h40020000 $project_name/axi_interc0_inst/AXIL_M03 \
+  $project_name/axi_spi0_inst/s_axi
+sbp_assign_addr_seg -offset 'h00300000 $project_name/axi_interc0_inst/AXI_M01 \
+  $project_name/sysmem_dmac0_inst/AXI_S0
+sbp_assign_addr_seg -offset 'h40010000 $project_name/axi_interc0_inst/AXIL_M02 \
+  $project_name/dmac0_inst/s_axi
+sbp_assign_addr_seg -offset 'h40030000 $project_name/axi_interc0_inst/AXIL_M04 \
+  $project_name/pwm0_inst/s_axi

projects/ad738x_fmc/lfcpnx/Makefile

@@ -0,0 +1,22 @@
+####################################################################################
+## Copyright (c) 2024 - 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad738x_fmc_lfcpnx
+
+M_DEPS += system_constr.pdc
+M_DEPS += ../../common/lfcpnx/lfcpnx_system_constr.pdc
+M_DEPS += ../../../projects/scripts/adi_pd.tcl
+M_DEPS += ../../../projects/common/lfcpnx/lfcpnx_system_pb.tcl
+M_DEPS += ../../../projects/ad738x_fmc/common/ad738x_pb.tcl
+
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_pwm_gen
+LIB_DEPS += spi_engine/axi_spi_engine
+LIB_DEPS += spi_engine/spi_engine_execution
+LIB_DEPS += spi_engine/spi_engine_interconnect
+LIB_DEPS += spi_engine/spi_engine_offload
+
+include ../../scripts/project-lattice.mk

projects/ad738x_fmc/lfcpnx/system_constr.pdc

@@ -0,0 +1,21 @@
+###############################################################################
+## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# spi_engine
+ldc_set_location -site {AD12} [get_ports cs];           #G7 FMC_LA00_CLK_N  PB112B_3
+ldc_set_location -site {AF4} [get_ports sdo];           #H7 FMC_LA02_P      PB150A_3
+ldc_set_location -site {Y5} [get_ports {sdi_bus[0]}];   #D8 FMC_LA01_CLK_P  PB148A_3
+ldc_set_location -site {AA5} [get_ports {sdi_bus[1]}];  #D9 FMC_LA01_CLK_N  PB148B_3
+ldc_set_location -site {AF3} [get_ports {sdi_bus[2]}];  #H8 FMC_LA02_N      PB150B_3
+ldc_set_location -site {AD4} [get_ports {sdi_bus[3]}];  #G9 FMC_LA03_P      PB152A_3
+ldc_set_location -site {AC12} [get_ports sclk];         #G6 FMC_LA00_CLK_P  PB112A_3
+
+ldc_set_port -iobuf {IO_TYPE=LVCMOS18H} [get_ports cs]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS18H} [get_ports sdo]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS18H} [get_ports {sdi_bus[0]}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS18H} [get_ports {sdi_bus[1]}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS18H} [get_ports {sdi_bus[2]}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS18H} [get_ports {sdi_bus[3]}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS18H} [get_ports sclk]

projects/ad738x_fmc/lfcpnx/system_pb.tcl

@@ -0,0 +1,10 @@
+###############################################################################
+## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+
+set timer_en 0
+source $ad_hdl_dir/projects/common/lfcpnx/lfcpnx_system_pb.tcl
+source $ad_hdl_dir/projects/ad738x_fmc/common/ad738x_pb.tcl

projects/ad738x_fmc/lfcpnx/system_project.tcl

@@ -0,0 +1,23 @@
+###############################################################################
+## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_lattice.tcl
+
+
+adi_project ad738x_fmc_lfcpnx
+adi_project_files_default ad738x_fmc_lfcpnx
+
+adi_project_files ad738x_fmc_lfcpnx -flist [list \
+  system_top.v \
+  ../../common/lfcpnx/lfcpnx_system_constr.pdc \
+  system_constr.pdc]
+
+adi_project_run ad738x_fmc_lfcpnx \
+  -cmd_list { \
+    {prj_clean_impl -impl $impl} \
+    {prj_set_strategy_value -strategy Strategy1 bit_ip_eval=True} \
+    {prj_set_strategy_value -strategy Strategy1 syn_frequency=100}
+  }

projects/ad738x_fmc/lfcpnx/system_project_pb.tcl

@@ -0,0 +1,9 @@
+###############################################################################
+## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_lattice_pb.tcl
+
+adi_project_pb ad738x_fmc_lfcpnx