axi_dmac: End cyclic transfers by lowering CYCLIC #1757
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This commit updates the DMA to end the cyclic transfers by lowering the CYCLIC flag when such a transfer is in progress. This allows for a smooth transition between different transfers, without having to disable the DMA. The DMA will also generate 1 SOT interrupt and 1 EOT interrupt to mark the limits of the cyclic transfer. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
podgori
requested review from
IuliaCMoldovan,
gastmaier and
StancaPop
as code owners
gastmaier
reviewed
Jul 14, 2025
| VERSION_MINOR | ||
| RO | ||
| ENDFIELD | ||
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| FIELD | ||
| [7:0] 0x00000064 | ||
| [7:0] 0x00000061 |
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It may be time to let a go, and set the patch number to 0.
proposal #1831
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PR Description
This PR updates the DMA to end the cyclic transfers by lowering the CYCLIC flag when such a transfer is in progress. This allows for a smooth transition between different transfers, without having to disable the DMA.
The DMA will also generate 1 SOT interrupt and 1 EOT interrupt to mark the limits of the cyclic transfer.
PR Type
PR Checklist