analogdevicesinc · BCapota · May 6, 2025 · Apr 15, 2025 · Apr 15, 2025
@@ -7,8 +7,8 @@ Overview
 -------------------------------------------------------------------------------
 
 This design allows controlling, receiving and transmitting sample stream
-from/to an ADRV9001/ADRV9002 device through two independent source-synchronous
-interfaces.
+from/to an :adi:`ADRV9002 <ADRV9002>` device through two independent
+source-synchronous interfaces.
 Supports both CMOS and LVDS interface, but not at the same time.
 The selection of the I/O standard must be done by setting a parameter before
 building the project.
@@ -18,11 +18,16 @@ in LVDS mode with 1 or 2 lanes. This is runtime configurable.
 The complete list of supported modes can be consulted in the
 :ref:`axi_adrv9001` Interface Core documentation.
 
-Supported devices
+Supported boards
 -------------------------------------------------------------------------------
 
 - :adi:`JUPITER_SDR <AD-JUPITER-EBZ>`
 
+Supported devices
+-------------------------------------------------------------------------------
+
+- :adi:`ADRV9002 <ADRV9002>`
+
 Block design
 -------------------------------------------------------------------------------
 

@@ -0,0 +1,15 @@
+# JUPITER_SDR HDL Project
+
+- Evaluation board product page: [AD-JUPITER-EBZ](https://www.analog.com/ad-jupiter-ebz)
+- System documentation: https://wiki.analog.com/resources/eval/user-guides/jupiter_sdr/reference_hdl 
+- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/jupiter_sdr/index.html
+
+## Supported parts
+
+| Part name                                      | Description                                                  |
+|------------------------------------------------|--------------------------------------------------------------|
+| [ADRV9002](https://www.analog.com/adrv9002)    | Wideband RF Transceiver and Dual Narrow-Band                 |
+
+## Building the project
+
+Please enter the folder for the FPGA carrier you want to use and read the README.md.