ad9656_fmc: Add VADJ value & fix build section

Signed-off-by: Stanca Pop <stanca.pop@analog.com>

Author: StancaPop

projects/ad9656_fmc/README.md

@@ -3,6 +3,7 @@
 - Evaluation board product page: [EVAL-AD9656](https://www.analog.com/eval-ad9656)
 - System documentation: https://wiki.analog.com/resources/eval/ad9656-125ebz
 - HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/ad9656_fmc/index.html
+- Evaluation board VADJ range: 1.2V - 2.5V
 
 ## Supported parts
 

projects/ad9656_fmc/zcu102/README.md

@@ -1,28 +1,26 @@
-# AD9656-FMC/ZCU102 HDL Project
+<!-- no_build_example, no_dts -->
 
-## Building the project
+# AD9656-FMC/ZCU102 HDL Project
 
-The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
+- VADJ with which it was tested in hardware: 1.8V
 
-:warning: **When changing the default configuration, the timing_constr.xdc constraints should be updated as well!**
+## Building the project
 
 ```
 cd projects/ad9656_fmc/zcu102
 make
 ```
 
-All of the RX link modes can be found in the [AD9656 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9656.pdf). We offer support for only a few of them.
-
-If other configurations are desired, then the parameters from the HDL project (see below) need to be changed, as well as the No-OS project configurations.
+All of the RX link modes can be found in the [AD9656 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9656.pdf). We offer support for one of them.
 
-The overwritable parameters from the environment are:
+This project is not parameterizable, it has a fixed configuration:
 
 - JESD_MODE - link layer encoder mode used; 
-  - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical layer
-- RX_JESD_M - RX number of converters per link, only 4 is supported
-- RX_JESD_L - RX number of lanes per link, default is 4 (Options: 1/2/4)
-- RX_JESD_S - RX number of samples per converter per frame, only 1 is supported
-- RX_JESD_NP - RX number of bits per sample, only 16 is supported
-- RX_SAMPLES_PER_CHANNEL - RX number of samples per channel, default is 2 (Computed as: L * 32 / (M * N))
+  - **8B10B** - 8b10b link layer defined in JESD204B, uses ADI IP as Physical layer
+- RX_JESD_M - **4**; RX number of converters per link
+- RX_JESD_L - **4**; RX number of lanes per link
+- RX_JESD_S - **1**; RX number of samples per converter per frame
+- RX_JESD_NP - **16**; RX number of bits per sample
+- RX_SAMPLES_PER_CHANNEL - **2**; RX number of samples per channel (Computed as: L * 32 / (M * N))
 
 Corresponding No-OS project: [ad9656_fmc](https://github.com/analogdevicesinc/no-OS/tree/main/projects/ad9656_fmc)