library: fix wrong reset polarity role for altera IP

Quartus detects reset polarity from the signal role, and inserts adapaters
automatically. The IP affected by this commit were previously assigning the
wrong (active high) polarity to active-low resets. This can cause multiple
problems.

The i3c controller and spi engine resets are generated by other IPs in the
framework, and these were also detected as wrong polarity, hence it being
undetected so far.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>

Author: LBFFilho

library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl

@@ -34,8 +34,8 @@ proc p_elaboration {} {
 
   # clock and reset interface
 
-  ad_interface clock  clk      input 1
-  ad_interface reset  reset_n  input 1 if_clk
+  ad_interface clock    clk      input 1
+  ad_interface reset-n  reset_n  input 1 if_clk
 
   add_interface sdo axi4stream end
   add_interface_port sdo sdo_ready tready output 1

library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_hw.tcl

@@ -66,7 +66,7 @@ proc p_elaboration {} {
     set if_clk if_clk
   }
 
-  ad_interface reset reset_n output 1 $if_clk
+  ad_interface reset-n reset_n output 1 $if_clk
 
   ad_interface signal offload_trigger input 1 if_pwm
 

library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl

@@ -52,7 +52,7 @@ proc p_elaboration {} {
   # Microprocessor interface
 
   ad_interface clock   up_clk    input                  1
-  ad_interface reset   up_rstn   input                  1   if_up_clk
+  ad_interface reset-n up_rstn   input                  1   if_up_clk
   ad_interface signal  up_wreq   input                  1
   ad_interface signal  up_wack   output                 1
   ad_interface signal  up_waddr  input                 14
@@ -115,8 +115,8 @@ proc p_elaboration {} {
 
   # SPI Engine interfaces
 
-  ad_interface clock spi_clk     input 1
-  ad_interface reset spi_resetn  output 1 if_spi_clk
+  ad_interface clock   spi_clk     input 1
+  ad_interface reset-n spi_resetn  output 1 if_spi_clk
 
   add_interface cmd axi4stream start
   add_interface_port cmd cmd_ready tready   input  1

library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl

@@ -32,7 +32,7 @@ proc p_elaboration {} {
   # clock and reset interface
 
   ad_interface clock   clk     input 1
-  ad_interface reset   resetn  input 1 if_clk
+  ad_interface reset-n resetn  input 1 if_clk
 
   ad_interface signal active output 1
 

library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl

@@ -23,8 +23,8 @@ proc p_elaboration {} {
 
   # clock and reset interface
 
-  ad_interface clock clk     input 1 
-  ad_interface reset resetn  input 1 if_clk
+  ad_interface clock    clk     input 1
+  ad_interface reset-n  resetn  input 1 if_clk
 
   # command master interface
 

library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl

@@ -32,7 +32,6 @@ proc p_elaboration {} {
   # control interface
 
   ad_interface clock ctrl_clk input 1
-  ad_interface reset spi_resetn  input 1 if_spi_clk
 
   add_interface ctrl_cmd_wr conduit end
   add_interface_port ctrl_cmd_wr ctrl_cmd_wr_en    wre   input  1
@@ -62,8 +61,8 @@ proc p_elaboration {} {
 
   # SPI Engine interfaces
 
-  ad_interface clock   spi_clk     input 1
-  ad_interface resetn  spi_resetn  input 1 if_spi_clk
+  ad_interface clock    spi_clk     input 1
+  ad_interface reset-n  spi_resetn  input 1 if_spi_clk
 
   ad_interface signal  trigger     input 1 if_pwm
 

library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl

@@ -27,8 +27,8 @@ proc p_elaboration {} {
 
 # clock and reset interface
 
-  ad_interface clock clk    input 1
-  ad_interface reset resetn input 1 if_clk
+  ad_interface clock    clk    input 1
+  ad_interface reset-n  resetn input 1 if_clk
 
   ad_interface signal spi_active input 1 active
   ad_interface signal data_ready output 1 if_pwm