Skip to content

Commit e2f45ef

Browse files
authored
docs: add docs/library/cn0363/* specific IPs
Adds documentation for the CN0363 specific IPs: - CN0363 DMA Sequencer; - CN0363 Phase Data Sync. Signed-off-by: Carlos Souza <carlos.souza@analog.com> Signed-off-by: Jorge Marques <jorge.marques@analog.com>
1 parent d6a904b commit e2f45ef

File tree

5 files changed

+255
-3
lines changed

5 files changed

+255
-3
lines changed
Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,117 @@
1+
.. _cn0363_dma_sequencer:
2+
3+
CN0363 DMA Sequencer
4+
================================================================================
5+
6+
.. hdl-component-diagram::
7+
8+
The CN0363 Sequencer FPGA Peripheral is part of the :ref:`cn0363`
9+
and is responsible to sequence the various data channels to the DMA.
10+
11+
Files
12+
--------------------------------------------------------------------------------
13+
14+
.. list-table::
15+
:header-rows: 1
16+
17+
* - Name
18+
- Description
19+
* - :git-hdl:`library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v`
20+
- Verilog source for the peripheral.
21+
* - :git-hdl:`library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl`
22+
- TCL script to generate the Vivado IP-integrator project for the
23+
peripheral.
24+
25+
Interface
26+
--------------------------------------------------------------------------------
27+
28+
.. hdl-interfaces::
29+
30+
* - clk
31+
- Clock
32+
- All other signals are synchronous to this clock.
33+
* - resetn
34+
- Synchronous active low reset
35+
- Resets the internal state machine of the core.
36+
* - phase
37+
- AXI-Stream slave
38+
- Phase data channel.
39+
* - data
40+
- AXI-Stream slave
41+
- Sample data channel.
42+
* - data_filtered
43+
- AXI-Stream slave
44+
- Filtered sample data channel.
45+
* - i_q
46+
- AXI-Stream slave
47+
- Demodulated I/Q sample data channel.
48+
* - i_q_filtered
49+
- AXI-Stream slave
50+
- Filtered demodulated I/Q sample data channel.
51+
* - dma_wr
52+
- FIFO Write Interface master
53+
- Low-level SPI bus interface that is controlled by peripheral.
54+
* - overflow
55+
- Output
56+
- The overflow signal is asserted if a overflow on the DMA interface is
57+
detected.
58+
* - channel_enable
59+
- Input
60+
- Data channel enable sequencer output enable.
61+
* - processing_resetn
62+
- Output
63+
- Reset signal for the processing pipeline
64+
65+
Detailed Description
66+
--------------------------------------------------------------------------------
67+
68+
The :adi:`CN0363` DMA sequencer core acts as a link between the :adi:`CN0363`
69+
processing pipeline and the connected DMA controller. On one side it accepts data
70+
from the processing pipeline and on the other side it sends the data to the DMA
71+
controller. The core is only active when the DMA controller signals that it is
72+
waiting for data, when it is inactive it also asserts the ``processing_resetn``
73+
signal to keep the processing pipeline in reset. Since the DMA is running at a
74+
much faster clock than the output data rate from the processing pipeline the
75+
different channels are time-division-multiplexed and send one by one to the DMA
76+
controller over the ``dma_wr`` interface.
77+
78+
When active, the core cycles through the input channels in the following order:
79+
80+
#. phase (Reference channel)
81+
#. data (Reference channel)
82+
#. data_filtered (Reference channel)
83+
#. i_q, I component (Reference channel)
84+
#. i_q, Q component (Reference channel)
85+
#. i_q_filtered, I component (Reference channel)
86+
#. i_q_filtered, Q component (Reference channel)
87+
#. phase (Sample channel)
88+
#. data (Sample channel)
89+
#. data_filtered (Sample channel)
90+
#. i_q, I component (Sample channel)
91+
#. i_q, Q component (Sample channel)
92+
#. i_q_filtered, I component (Sample channel)
93+
#. i_q_filtered, Q component (Sample channel)
94+
95+
Each of these has a corresponding bit in the ``channel_enable`` and only if the
96+
bit is set, the channel is sent to the ``dma_wr`` interface, otherwise it is
97+
discarded. This allows an application to select which data channels it wants to
98+
capture.
99+
100+
Software Support
101+
--------------------------------------------------------------------------------
102+
103+
* Linux device driver at :git-linux:`drivers/iio/adc/ad7173.c`
104+
* Linux device driver documentation at :dokuwiki:`Linux Device Drivers <resources/eval/user-guides/eval-cn0363-pmdz/software/linux/drivers>`
105+
* No-OS device driver at :git-no-os:`drivers/adc/ad717x`
106+
* No-OS device driver documentation at :dokuwiki:`AD717X No-OS Software Drivers <resources/tools-software/uc-drivers/ad717x>`
107+
108+
References
109+
--------------------------------------------------------------------------------
110+
111+
* HDL IP Core at :git-hdl:`library/cn0363/cn0363_dma_sequencer`
112+
* HDL project at :git-hdl:`projects/cn0363`
113+
* HDL project documentation at :ref:`cn0363`
114+
* :adi:`CN0363`
115+
* :adi:`AD7175-2`
116+
* :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`
117+
* :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`
Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,112 @@
1+
.. _cn0363_phase_data_sync:
2+
3+
CN0363 Phase Data Sync
4+
================================================================================
5+
6+
.. hdl-component-diagram::
7+
8+
The :adi:`CN0363` Phase Data Sync FPGA Peripheral is part of the
9+
:ref:`EVAL-CN0363-PMDZ HDL reference design <cn0363>` and is responsible for
10+
preparing the ADC conversion result data and aligning it with the phase and
11+
feeding both to the processing pipeline.
12+
13+
Files
14+
--------------------------------------------------------------------------------
15+
16+
.. list-table::
17+
:header-rows: 1
18+
19+
* - Name
20+
- Description
21+
* - :git-hdl:`/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v`
22+
- Verilog source for the peripheral.
23+
* - :git-hdl:`/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl`
24+
- TCL script to generate the Vivado IP-integrator project for the
25+
peripheral.
26+
27+
Interface
28+
--------------------------------------------------------------------------------
29+
30+
.. hdl-interfaces::
31+
32+
* - clk
33+
- Clock
34+
- All other signals are synchronous to this clock.
35+
* - resetn
36+
- Synchronous active low reset
37+
- Resets the internal state machine of the core.
38+
* - processing_resetn
39+
- Synchronous active low reset
40+
- Indicator that the processing pipeline is in reset.
41+
* - S_AXIS_SAMPLE
42+
- AXI-Stream slave
43+
- Input sample data stream
44+
* - M_AXIS_SAMPLE
45+
- AXI-Stream master
46+
- Output sample data stream
47+
* - M_AXIS_PHASE
48+
- AXI-Stream master
49+
- Output phase data stream
50+
* - sample_has_stat
51+
- Input
52+
- Whether the incoming data on ``S_AXIS_SAMPLE`` has the STAT register
53+
appended.
54+
* - conv_done
55+
- Input
56+
- Conversion done signal from the ADC.
57+
* - phase
58+
- Input
59+
- Current excitation signal phase.
60+
* - overflow
61+
- Input
62+
- The overflow signal is asserted if a new sample arrives before the
63+
previous one has been consumed.
64+
65+
Detailed Description
66+
--------------------------------------------------------------------------------
67+
68+
The :adi:`CN0363` Phase Data Sync FPGA Peripheral takes the raw ADC sample data
69+
read by a SPI controller from the ADC on the S_AXIS_SAMPLE stream. The data is
70+
assembled into 24-bit word and converted from offset binary to two's complement
71+
signed.
72+
73+
When a rising edge is detected on the ``conv_done signal`` the core takes a
74+
snapshot of the phase input signal. This data will be assumed to the phase
75+
that belongs to the next incoming data sample on the S_AXIS_SAMPLE. The data
76+
is aligned with the corresponding phase data and both are send out on the
77+
``M_AXIS_SAMPLE`` and ``M_AXIS_PHASE stream``.
78+
79+
If the ``sample_has_stat`` signal is asserted the core will receive 32-bit
80+
instead of 24-bit per sample on the S_AXIS_SAMPLE stream. The last 8-bit are
81+
assumed to contain the STAT register of the ADC, which among other things
82+
contains the information about which channel the ADC result belongs to. This
83+
information can be used to detect and fix channel swaps. If
84+
``sample_has_stat`` is not asserted the core assumes that no channel swaps
85+
happen and the whole pipeline is always running fast enough to accept a
86+
sample before the next one is ready.
87+
88+
If ``processing_resetn`` is asserted the processing pipeline is assumed to be
89+
in reset and incapable of accepting new samples and when a new sample arrives at
90+
the ``S_AXIS_SAMPLE`` port a overflow condition is generated. The signal also
91+
resets the channel swap detection logic and makes sure that the next sample that
92+
is inserted into the processing pipeline after the reset belongs to the first
93+
channel.
94+
95+
Software Support
96+
--------------------------------------------------------------------------------
97+
98+
* Linux device driver at :git-linux:`drivers/iio/adc/ad7173.c`
99+
* Linux device driver documentation at :dokuwiki:`Linux Device Drivers <resources/eval/user-guides/eval-cn0363-pmdz/software/linux/drivers>`
100+
* No-OS device driver at :git-no-os:`drivers/adc/ad717x`
101+
* No-OS device driver documentation at :dokuwiki:`AD717X No-OS Software Drivers <resources/tools-software/uc-drivers/ad717x>`
102+
103+
References
104+
--------------------------------------------------------------------------------
105+
106+
* HDL IP Core at :git-hdl:`library/cn0363/cn0363_phase_data_sync`
107+
* HDL project at :git-hdl:`projects/cn0363`
108+
* HDL project documentation at :ref:`cn0363`
109+
* :adi:`CN0363`
110+
* :adi:`AD7175-2`
111+
* :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`
112+
* :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`

docs/library/cn0363/index.rst

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
.. _cn0363_lib:
2+
3+
CN0363
4+
================================================================================
5+
6+
The CN0363 library is comprised by two IPs:
7+
8+
- :doc:`cn0363_dma_sequencer`
9+
- :doc:`cn0363_phase_data_sync`
10+
11+
:git-hdl:`CN0363 DMA Sequencer <library/cn0363/cn0363_dma_sequencer>` core acts
12+
as a link between the CN0363 processing pipeline and the connected DMA
13+
controller. :git-hdl:`CN0363 Phase Data Sync <library/cn0363/cn0363_phase_data_sync>`
14+
core assembles the raw ADC sample data into a 24-bit word and converts it into
15+
two's complement format.
16+
17+
.. toctree::
18+
:maxdepth: 2
19+
:hidden:
20+
:glob:
21+
22+
*

docs/library/index.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,7 @@ Utilities
8383
axi_pwm_gen/index
8484
axi_sysid/index
8585
axi_tdd/index
86+
cn0363/index
8687
common/ad_dds/index
8788
corundum/index
8889
util_axis_fifo/index

docs/projects/cn0363/index.rst

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,7 @@ HDL related
211211
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
212212

213213
- :git-hdl:`CN0363_PMDZ HDL project source code <projects/cn0363>`
214-
- :dokuwiki:`[Wiki] CN0540 HDL project documentation <resources/eval/user-guides/eval-cn0363-pmdz/reference_hdl>`
214+
- :dokuwiki:`[Wiki] CN0363 HDL project documentation <resources/eval/user-guides/eval-cn0363-pmdz/reference_hdl>`
215215

216216
.. list-table::
217217
:widths: 30 35 35
@@ -240,10 +240,10 @@ HDL related
240240
- :ref:`axi_sysid`
241241
* - CN0363_DMA_SEQUENCER
242242
- :git-hdl:`library/cn0363/cn0363_dma_sequencer`
243-
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/cn0363/sequencer>`
243+
- :ref:`cn0363_dma_sequencer`
244244
* - CN0363_PHASE_DATA_SYNC
245245
- :git-hdl:`library/cn0363/cn0363_phase_data_sync`
246-
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/cn0363/phase_data_sync>`
246+
- :ref:`cn0363_phase_data_sync`
247247
* - CORDIC_DEMOD
248248
- :git-hdl:`library/cordic_demod`
249249
- ---

0 commit comments

Comments
 (0)