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| 1 | +.. _cn0363_dma_sequencer: |
| 2 | + |
| 3 | +CN0363 DMA Sequencer |
| 4 | +================================================================================ |
| 5 | + |
| 6 | +.. hdl-component-diagram:: |
| 7 | + |
| 8 | +The CN0363 Sequencer FPGA Peripheral is part of the :ref:`cn0363` |
| 9 | +and is responsible to sequence the various data channels to the DMA. |
| 10 | + |
| 11 | +Files |
| 12 | +-------------------------------------------------------------------------------- |
| 13 | + |
| 14 | +.. list-table:: |
| 15 | + :header-rows: 1 |
| 16 | + |
| 17 | + * - Name |
| 18 | + - Description |
| 19 | + * - :git-hdl:`library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v` |
| 20 | + - Verilog source for the peripheral. |
| 21 | + * - :git-hdl:`library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl` |
| 22 | + - TCL script to generate the Vivado IP-integrator project for the |
| 23 | + peripheral. |
| 24 | + |
| 25 | +Interface |
| 26 | +-------------------------------------------------------------------------------- |
| 27 | + |
| 28 | +.. hdl-interfaces:: |
| 29 | + |
| 30 | + * - clk |
| 31 | + - Clock |
| 32 | + - All other signals are synchronous to this clock. |
| 33 | + * - resetn |
| 34 | + - Synchronous active low reset |
| 35 | + - Resets the internal state machine of the core. |
| 36 | + * - phase |
| 37 | + - AXI-Stream slave |
| 38 | + - Phase data channel. |
| 39 | + * - data |
| 40 | + - AXI-Stream slave |
| 41 | + - Sample data channel. |
| 42 | + * - data_filtered |
| 43 | + - AXI-Stream slave |
| 44 | + - Filtered sample data channel. |
| 45 | + * - i_q |
| 46 | + - AXI-Stream slave |
| 47 | + - Demodulated I/Q sample data channel. |
| 48 | + * - i_q_filtered |
| 49 | + - AXI-Stream slave |
| 50 | + - Filtered demodulated I/Q sample data channel. |
| 51 | + * - dma_wr |
| 52 | + - FIFO Write Interface master |
| 53 | + - Low-level SPI bus interface that is controlled by peripheral. |
| 54 | + * - overflow |
| 55 | + - Output |
| 56 | + - The overflow signal is asserted if a overflow on the DMA interface is |
| 57 | + detected. |
| 58 | + * - channel_enable |
| 59 | + - Input |
| 60 | + - Data channel enable sequencer output enable. |
| 61 | + * - processing_resetn |
| 62 | + - Output |
| 63 | + - Reset signal for the processing pipeline |
| 64 | + |
| 65 | +Detailed Description |
| 66 | +-------------------------------------------------------------------------------- |
| 67 | + |
| 68 | +The :adi:`CN0363` DMA sequencer core acts as a link between the :adi:`CN0363` |
| 69 | +processing pipeline and the connected DMA controller. On one side it accepts data |
| 70 | +from the processing pipeline and on the other side it sends the data to the DMA |
| 71 | +controller. The core is only active when the DMA controller signals that it is |
| 72 | +waiting for data, when it is inactive it also asserts the ``processing_resetn`` |
| 73 | +signal to keep the processing pipeline in reset. Since the DMA is running at a |
| 74 | +much faster clock than the output data rate from the processing pipeline the |
| 75 | +different channels are time-division-multiplexed and send one by one to the DMA |
| 76 | +controller over the ``dma_wr`` interface. |
| 77 | + |
| 78 | +When active, the core cycles through the input channels in the following order: |
| 79 | + |
| 80 | +#. phase (Reference channel) |
| 81 | +#. data (Reference channel) |
| 82 | +#. data_filtered (Reference channel) |
| 83 | +#. i_q, I component (Reference channel) |
| 84 | +#. i_q, Q component (Reference channel) |
| 85 | +#. i_q_filtered, I component (Reference channel) |
| 86 | +#. i_q_filtered, Q component (Reference channel) |
| 87 | +#. phase (Sample channel) |
| 88 | +#. data (Sample channel) |
| 89 | +#. data_filtered (Sample channel) |
| 90 | +#. i_q, I component (Sample channel) |
| 91 | +#. i_q, Q component (Sample channel) |
| 92 | +#. i_q_filtered, I component (Sample channel) |
| 93 | +#. i_q_filtered, Q component (Sample channel) |
| 94 | + |
| 95 | +Each of these has a corresponding bit in the ``channel_enable`` and only if the |
| 96 | +bit is set, the channel is sent to the ``dma_wr`` interface, otherwise it is |
| 97 | +discarded. This allows an application to select which data channels it wants to |
| 98 | +capture. |
| 99 | + |
| 100 | +Software Support |
| 101 | +-------------------------------------------------------------------------------- |
| 102 | + |
| 103 | +* Linux device driver at :git-linux:`drivers/iio/adc/ad7173.c` |
| 104 | +* Linux device driver documentation at :dokuwiki:`Linux Device Drivers <resources/eval/user-guides/eval-cn0363-pmdz/software/linux/drivers>` |
| 105 | +* No-OS device driver at :git-no-os:`drivers/adc/ad717x` |
| 106 | +* No-OS device driver documentation at :dokuwiki:`AD717X No-OS Software Drivers <resources/tools-software/uc-drivers/ad717x>` |
| 107 | + |
| 108 | +References |
| 109 | +-------------------------------------------------------------------------------- |
| 110 | + |
| 111 | +* HDL IP Core at :git-hdl:`library/cn0363/cn0363_dma_sequencer` |
| 112 | +* HDL project at :git-hdl:`projects/cn0363` |
| 113 | +* HDL project documentation at :ref:`cn0363` |
| 114 | +* :adi:`CN0363` |
| 115 | +* :adi:`AD7175-2` |
| 116 | +* :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>` |
| 117 | +* :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>` |
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