convert used with Component does not handle constant signals

[rroohhh]

Running

from amaranth import *
from amaranth.back.verilog import convert
from amaranth.lib import stream
from amaranth.lib.wiring import In, Component

class A(Component):
    a: In(stream.Signature(1, always_valid=True))

    def elaborate(self, _):
        m = Module()
        return m


print(convert(A()))

produces

Traceback (most recent call last):
  File "/tmp/a.py", line 16, in <module>
    print(convert(A()))
  File "/home/robin/.guix-home/profile/lib/python3.10/site-packages/amaranth/back/verilog.py", line 61, in convert
    verilog_text, name_map = convert_fragment(fragment, ports, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs, **kwargs)
  File "/home/robin/.guix-home/profile/lib/python3.10/site-packages/amaranth/back/verilog.py", line 39, in convert_fragment
    rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
  File "/home/robin/.guix-home/profile/lib/python3.10/site-packages/amaranth/back/rtlil.py", line 1275, in convert_fragment
    netlist = _ir.build_netlist(fragment, ports=ports, name=name, **kwargs)
  File "/home/robin/.guix-home/profile/lib/python3.10/site-packages/amaranth/hdl/_ir.py", line 1777, in build_netlist
    design = fragment.prepare(ports=ports, hierarchy=(name,), **kwargs)
  File "/home/robin/.guix-home/profile/lib/python3.10/site-packages/amaranth/hdl/_ir.py", line 218, in prepare
    ports = self._prepare_ports(ports)
  File "/home/robin/.guix-home/profile/lib/python3.10/site-packages/amaranth/hdl/_ir.py", line 211, in _prepare_ports
    raise TypeError(f"Only signals and IO ports may be added as ports, not {signal!r}")
TypeError: Only signals and IO ports may be added as ports, not (const 1'd1)