Skip to content

Commit d15705c

Browse files
rroohhhwhitequark
authored andcommitted
lib.fifo: use proper clock domains in AsyncFIFO tests
1 parent 76efe86 commit d15705c

File tree

1 file changed

+4
-4
lines changed

1 file changed

+4
-4
lines changed

tests/test_lib_fifo.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -312,16 +312,16 @@ def write_process():
312312
for i in range(fill_in):
313313
yield fifo.w_data.eq(i)
314314
yield fifo.w_en.eq(1)
315-
yield
315+
yield Tick("write")
316316
yield fifo.w_en.eq(0)
317-
yield
318-
yield
317+
yield Tick("write")
318+
yield Tick("write")
319319
self.assertEqual((yield fifo.w_level), expected_level)
320320
yield write_done.eq(1)
321321

322322
def read_process():
323323
while not (yield write_done):
324-
yield
324+
yield Tick("read")
325325
self.assertEqual((yield fifo.r_level), expected_level)
326326

327327
simulator = Simulator(fifo)

0 commit comments

Comments
 (0)