hdl.rec: remove.

Fixes #879.

Author: wanda-phi

amaranth/__init__.py

@@ -21,6 +21,5 @@
     "ClockDomain",
     "Elaboratable", "Fragment", "Instance",
     "Memory",
-    "Record",
     "DomainRenamer", "ResetInserter", "EnableInserter",
 ]

amaranth/hdl/__init__.py

@@ -10,7 +10,6 @@
 from ._ir import Instance, IOBufferInstance
 from ._mem import MemoryData, MemoryInstance, Memory, ReadPort, WritePort, DummyPort
 from ._nir import CombinationalCycle
-from ._rec import Record
 from ._xfrm import DomainRenamer, ResetInserter, EnableInserter
 
 
@@ -33,8 +32,6 @@
     "CombinationalCycle",
     # _mem
     "MemoryData", "MemoryInstance", "Memory", "ReadPort", "WritePort", "DummyPort",
-    # _rec
-    "Record",
     # _xfrm
     "DomainRenamer", "ResetInserter", "EnableInserter",
 ]

amaranth/hdl/_ast.py

@@ -2352,19 +2352,6 @@ class Array(MutableSequence):
         b = Signal.range(10)
         r = Signal(8)
         m.d.comb += r.eq(mult[a][b])
-
-    Array of records::
-
-        layout = [
-            ("r_data", 16),
-            ("r_en",   1),
-        ]
-        buses  = Array(Record(layout) for busno in range(4))
-        master = Record(layout)
-        m.d.comb += [
-            buses[sel].r_en.eq(master.r_en),
-            master.r_data.eq(buses[sel].r_data),
-        ]
     """
     def __init__(self, iterable=()):
         self._inner    = list(iterable)

amaranth/hdl/_rec.py

@@ -3,7 +3,7 @@
 import argparse
 import importlib
 
-from .hdl import Signal, Record, Elaboratable
+from .hdl import Signal, Elaboratable
 from .back import rtlil
 
 
@@ -69,10 +69,9 @@ def _serve_yosys(modules):
             try:
                 elaboratable = modules[module_name](*args, **kwargs)
                 ports = []
-                # By convention, any public attribute that is a Signal or a Record is
-                # considered a port.
+                # By convention, any public attribute that is a Signal is considered a port.
                 for port_name, port in vars(elaboratable).items():
-                    if not port_name.startswith("_") and isinstance(port, (Signal, Record)):
+                    if not port_name.startswith("_") and isinstance(port, Signal):
                         ports += port._lhs_signals()
                 rtlil_text = rtlil.convert(elaboratable, name=module_name, ports=ports)
                 response = {"frontend": "ilang", "source": rtlil_text}

amaranth/hdl/rec.py

@@ -23,6 +23,14 @@ Version 0.6 (unreleased)
 ========================
 
 
+Language changes
+----------------
+
+.. currentmodule:: amaranth.hdl
+
+* Removed (deprecated in 0.4): :class:`Record`.
+
+
 Standard library changes
 ------------------------
 

amaranth/rpc.py

@@ -72,7 +72,6 @@ The prelude exports exactly the following names:
 * :class:`Fragment`
 * :class:`Instance`
 * :class:`Memory`
-* :class:`Record` (deprecated)
 * :class:`DomainRenamer`
 * :class:`ResetInserter`
 * :class:`EnableInserter`