Implement RFC 27 amendment: deprecate add_sync_process, not add_process.

wanda-phi · whitequark · commit 4014f6429c97 · 2024-02-12T18:26:48.000Z
diff --git a/amaranth/sim/core.py b/amaranth/sim/core.py
@@ -80,7 +80,6 @@ def _check_process(self, process):
                             .format(process))
         return process
 
-    @deprecated("The `add_process` method is deprecated per RFC 27. Use `add_testbench` instead.")
     def add_process(self, process):
         process = self._check_process(process)
         def wrapper():
@@ -89,6 +88,7 @@ def wrapper():
             yield from process()
         self._engine.add_coroutine_process(wrapper, default_cmd=None)
 
+    @deprecated("The `add_sync_process` method is deprecated per RFC 47. Use `add_process` or `add_testbench` instead.")
     def add_sync_process(self, process, *, domain="sync"):
         process = self._check_process(process)
         def wrapper():
@@ -107,25 +107,6 @@ def wrapper():
                 except StopIteration:
                     break
                 try:
-                    if isinstance(command, (Settle, Delay, Tick)):
-                        frame = generator.gi_frame
-                        module_globals = frame.f_globals
-                        if '__name__' in module_globals:
-                            module = module_globals['__name__']
-                        else:
-                            module = "<string>"
-                        # If the warning action is "error", this call will throw the warning, and
-                        # the try block will redirect it into the generator.
-                        warnings.warn_explicit(
-                            f"Using `{command.__class__.__name__}` is deprecated within "
-                            f"`add_sync_process` per RFC 27; use `add_testbench` instead.",
-                            DeprecationWarning,
-                            filename=frame.f_code.co_filename,
-                            lineno=frame.f_lineno,
-                            module=module,
-                            registry=module_globals.setdefault("__warningregistry__", {}),
-                            module_globals=module_globals,
-                        )
                     result = yield command
                     exception = None
                 except Exception as e:
diff --git a/docs/changes.rst b/docs/changes.rst
@@ -29,9 +29,8 @@ Apply the following changes to code written against Amaranth 0.4 to migrate it t
 * Replace uses of ``Value.matches()`` with no patterns with ``Const(1)``
 * Update uses of ``amaranth.utils.log2_int(need_pow2=False)`` to :func:`amaranth.utils.ceil_log2`
 * Update uses of ``amaranth.utils.log2_int(need_pow2=True)`` to :func:`amaranth.utils.exact_log2`
-* Update uses of ``Simulator.add_process`` to ``Simulator.add_testbench``
 * Convert uses of ``Simulator.add_sync_process`` used as testbenches to ``Simulator.add_testbench``
-* Convert uses of ``yield Tick()`` within remaining ``Simulator.add_sync_process`` to plain ``yield``
+* Convert other uses of ``Simulator.add_sync_process`` to ``Simulator.add_process``
 
 
 Implemented RFCs
@@ -81,7 +80,7 @@ Toolchain changes
 
 * Added: ``Simulator.add_testbench``. (`RFC 27`_)
 * Deprecated: ``Settle`` simulation command. (`RFC 27`_)
-* Deprecated: ``Simulator.add_process``. (`RFC 27`_)
+* Deprecated: ``Simulator.add_sync_process``. (`RFC 27`_)
 * Removed: (deprecated in 0.4) use of mixed-case toolchain environment variable names, such as ``NMIGEN_ENV_Diamond`` or ``AMARANTH_ENV_Diamond``; use upper-case environment variable names, such as ``AMARANTH_ENV_DIAMOND``.
 
 
diff --git a/examples/basic/ctr_en.py b/examples/basic/ctr_en.py
@@ -23,12 +23,12 @@ def elaborate(self, platform):
 sim = Simulator(ctr)
 sim.add_clock(1e-6)
 def ce_proc():
-    yield; yield; yield
+    yield Tick(); yield Tick(); yield Tick()
     yield ctr.en.eq(1)
-    yield; yield; yield
+    yield Tick(); yield Tick(); yield Tick()
     yield ctr.en.eq(0)
-    yield; yield; yield
+    yield Tick(); yield Tick(); yield Tick()
     yield ctr.en.eq(1)
-sim.add_sync_process(ce_proc)
+sim.add_testbench(ce_proc)
 with sim.write_vcd("ctrl.vcd", "ctrl.gtkw", traces=[ctr.en, ctr.v, ctr.o]):
     sim.run_until(100e-6, run_passive=True)
diff --git a/tests/test_lib_cdc.py b/tests/test_lib_cdc.py
@@ -26,13 +26,13 @@ def test_basic(self):
         def process():
             self.assertEqual((yield o), 0)
             yield i.eq(1)
-            yield
+            yield Tick()
             self.assertEqual((yield o), 0)
-            yield
+            yield Tick()
             self.assertEqual((yield o), 0)
-            yield
+            yield Tick()
             self.assertEqual((yield o), 1)
-        sim.add_sync_process(process)
+        sim.add_process(process)
         sim.run()
 
     def test_reset_value(self):
@@ -45,13 +45,13 @@ def test_reset_value(self):
         def process():
             self.assertEqual((yield o), 1)
             yield i.eq(0)
-            yield
+            yield Tick()
             self.assertEqual((yield o), 1)
-            yield
+            yield Tick()
             self.assertEqual((yield o), 1)
-            yield
+            yield Tick()
             self.assertEqual((yield o), 0)
-        sim.add_sync_process(process)
+        sim.add_process(process)
         sim.run()
 
 
@@ -221,17 +221,17 @@ def process():
             yield ps.i.eq(0)
             # TODO: think about reset
             for n in range(5):
-                yield
+                yield Tick()
             # Make sure no pulses are generated in quiescent state
             for n in range(3):
-                yield
+                yield Tick()
                 self.assertEqual((yield ps.o), 0)
             # Check conservation of pulses
             accum = 0
             for n in range(10):
                 yield ps.i.eq(1 if n < 4 else 0)
-                yield
+                yield Tick()
                 accum += yield ps.o
             self.assertEqual(accum, 4)
-        sim.add_sync_process(process)
+        sim.add_process(process)
         sim.run()
diff --git a/tests/test_lib_crc.py b/tests/test_lib_crc.py
@@ -243,13 +243,13 @@ def process():
                     yield crc.start.eq(word == b"1")
                     yield crc.data.eq(word)
                     yield crc.valid.eq(1)
-                    yield
+                    yield Tick()
                 yield crc.valid.eq(0)
-                yield
+                yield Tick()
                 self.assertEqual((yield crc.crc), check)
 
             sim = Simulator(crc)
-            sim.add_sync_process(process)
+            sim.add_testbench(process)
             sim.add_clock(1e-6)
             sim.run()
 
@@ -283,18 +283,18 @@ def test_crc_words(self):
 
                 def process():
                     yield crc.start.eq(1)
-                    yield
+                    yield Tick()
                     yield crc.start.eq(0)
                     for word in words:
                         yield crc.data.eq(word)
                         yield crc.valid.eq(1)
-                        yield
+                        yield Tick()
                     yield crc.valid.eq(0)
-                    yield
+                    yield Tick()
                     self.assertEqual((yield crc.crc), check)
 
                 sim = Simulator(crc)
-                sim.add_sync_process(process)
+                sim.add_testbench(process)
                 sim.add_clock(1e-6)
                 sim.run()
 
@@ -334,17 +334,17 @@ def test_crc_match(self):
 
             def process():
                 yield crc.start.eq(1)
-                yield
+                yield Tick()
                 yield crc.start.eq(0)
                 for word in words:
                     yield crc.data.eq(word)
                     yield crc.valid.eq(1)
-                    yield
+                    yield Tick()
                 yield crc.valid.eq(0)
-                yield
+                yield Tick()
                 self.assertTrue((yield crc.match_detected))
 
             sim = Simulator(crc)
-            sim.add_sync_process(process)
+            sim.add_testbench(process)
             sim.add_clock(1e-6)
             sim.run()
diff --git a/tests/test_lib_fifo.py b/tests/test_lib_fifo.py
@@ -325,7 +325,7 @@ def testbench():
             for i in range(10):
                 yield fifo.w_data.eq(i)
                 yield fifo.w_en.eq(1)
-                yield
+                yield Tick()
 
                 if (i - ff_syncronizer_latency) > 0:
                     self.assertEqual((yield fifo.r_level), i - ff_syncronizer_latency)
@@ -334,7 +334,7 @@ def testbench():
 
         simulator = Simulator(fifo)
         simulator.add_clock(100e-6)
-        simulator.add_sync_process(testbench)
+        simulator.add_process(testbench)
         simulator.run()
 
     def check_async_fifo_level(self, fifo, fill_in, expected_level, read=False):
@@ -344,25 +344,24 @@ def write_process():
             for i in range(fill_in):
                 yield fifo.w_data.eq(i)
                 yield fifo.w_en.eq(1)
-                yield
+                yield Tick("write")
             yield fifo.w_en.eq(0)
-            yield
-            yield
+            yield Tick ("write")
             self.assertEqual((yield fifo.w_level), expected_level)
             yield write_done.eq(1)
 
         def read_process():
             if read:
                 yield fifo.r_en.eq(1)
             while not (yield write_done):
-                yield
+                yield Tick("read")
             self.assertEqual((yield fifo.r_level), expected_level)
 
         simulator = Simulator(fifo)
         simulator.add_clock(100e-6, domain="write")
-        simulator.add_sync_process(write_process, domain="write")
+        simulator.add_testbench(write_process)
         simulator.add_clock(50e-6, domain="read")
-        simulator.add_sync_process(read_process, domain="read")
+        simulator.add_testbench(read_process)
         with simulator.write_vcd("test.vcd"):
             simulator.run()
 
diff --git a/tests/test_sim.py b/tests/test_sim.py
