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hdl: remove Repl per RFC 10.
Closes #770.
1 parent 4da8adf commit 357ffb6

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6 files changed

+5
-58
lines changed

6 files changed

+5
-58
lines changed

amaranth/__init__.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
# must be kept in sync with docs/reference.rst!
1616
__all__ = [
1717
"Shape", "unsigned", "signed",
18-
"Value", "Const", "C", "Mux", "Cat", "Repl", "Array", "Signal", "ClockSignal", "ResetSignal",
18+
"Value", "Const", "C", "Mux", "Cat", "Array", "Signal", "ClockSignal", "ResetSignal",
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"Module",
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"ClockDomain",
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"Elaboratable", "Fragment", "Instance",

amaranth/hdl/__init__.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
from ._ast import Shape, unsigned, signed, ShapeCastable, ShapeLike
22
from ._ast import Value, ValueCastable, ValueLike
3-
from ._ast import Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
3+
from ._ast import Const, C, Mux, Cat, Array, Signal, ClockSignal, ResetSignal
44
from ._dsl import SyntaxError, SyntaxWarning, Module
55
from ._cd import DomainError, ClockDomain
66
from ._ir import UnusedElaboratable, Elaboratable, DriverConflict, Fragment, Instance
@@ -13,7 +13,7 @@
1313
# _ast
1414
"Shape", "unsigned", "signed", "ShapeCastable", "ShapeLike",
1515
"Value", "ValueCastable", "ValueLike",
16-
"Const", "C", "Mux", "Cat", "Repl", "Array", "Signal", "ClockSignal", "ResetSignal",
16+
"Const", "C", "Mux", "Cat", "Array", "Signal", "ClockSignal", "ResetSignal",
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# _dsl
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"SyntaxError", "SyntaxWarning", "Module",
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# _cd

amaranth/hdl/_ast.py

Lines changed: 1 addition & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

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__all__ = [
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"Shape", "signed", "unsigned", "ShapeCastable", "ShapeLike",
19-
"Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", "Slice", "Cat", "Repl",
19+
"Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", "Slice", "Cat",
2020
"Array", "ArrayProxy",
2121
"Signal", "ClockSignal", "ResetSignal",
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"ValueCastable", "ValueLike",
@@ -1170,37 +1170,6 @@ def __repr__(self):
11701170
return "(cat {})".format(" ".join(map(repr, self.parts)))
11711171

11721172

1173-
# TODO(amaranth-0.5): remove
1174-
@deprecated("instead of `Repl(value, count)`, use `value.replicate(count)`")
1175-
def Repl(value, count):
1176-
"""Replicate a value
1177-
1178-
An input value is replicated (repeated) several times
1179-
to be used on the RHS of assignments::
1180-
1181-
len(Repl(s, n)) == len(s) * n
1182-
1183-
Parameters
1184-
----------
1185-
value : Value, in
1186-
Input value to be replicated.
1187-
count : int
1188-
Number of replications.
1189-
1190-
Returns
1191-
-------
1192-
Value, out
1193-
Replicated value.
1194-
"""
1195-
if isinstance(value, int) and value not in [0, 1]:
1196-
warnings.warn("Value argument of Repl() is a bare integer {} used in bit vector "
1197-
"context; consider specifying explicit width using C({}, {}) instead"
1198-
.format(value, value, bits_for(value)),
1199-
SyntaxWarning, stacklevel=3)
1200-
1201-
return Value.cast(value).replicate(count)
1202-
1203-
12041173
class _SignalMeta(ABCMeta):
12051174
def __call__(cls, shape=None, src_loc_at=0, **kwargs):
12061175
signal = super().__call__(shape, **kwargs, src_loc_at=src_loc_at + 1)

amaranth/hdl/ast.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66

77
__all__ = [
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"Shape", "signed", "unsigned", "ShapeCastable", "ShapeLike",
9-
"Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", "Slice", "Cat", "Repl",
9+
"Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", "Slice", "Cat",
1010
"Array", "ArrayProxy",
1111
"Signal", "ClockSignal", "ResetSignal",
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"ValueCastable", "ValueLike",

docs/reference.rst

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,6 @@ The prelude exports exactly the following names:
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* :func:`C`
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* :func:`Mux`
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* :class:`Cat`
62-
* :class:`Repl` (deprecated)
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* :class:`Array`
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* :class:`Signal`
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* :class:`ClockSignal`

tests/test_hdl_ast.py

Lines changed: 0 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -970,27 +970,6 @@ def test_const(self):
970970
self.assertEqual(a.signed, False)
971971

972972

973-
class ReplTestCase(FHDLTestCase):
974-
@_ignore_deprecated
975-
def test_cast(self):
976-
r = Repl(0, 3)
977-
self.assertEqual(repr(r), "(cat (const 1'd0) (const 1'd0) (const 1'd0))")
978-
979-
@_ignore_deprecated
980-
def test_int_01(self):
981-
with warnings.catch_warnings():
982-
warnings.filterwarnings(action="error", category=SyntaxWarning)
983-
Repl(0, 3)
984-
Repl(1, 3)
985-
986-
@_ignore_deprecated
987-
def test_int_wrong(self):
988-
with self.assertWarnsRegex(SyntaxWarning,
989-
r"^Value argument of Repl\(\) is a bare integer 2 used in bit vector context; "
990-
r"consider specifying explicit width using C\(2, 2\) instead$"):
991-
Repl(2, 3)
992-
993-
994973
class ArrayTestCase(FHDLTestCase):
995974
def test_acts_like_array(self):
996975
a = Array([1,2,3])

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