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wanda-phiwhitequark
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hdl._ir: Fix fallout from #1190, add more tests.
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3 files changed

+43
-6
lines changed

3 files changed

+43
-6
lines changed

amaranth/hdl/_ir.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -772,7 +772,7 @@ def connect(self, lhs: _nir.Value, rhs: _nir.Value, *, src_loc):
772772
signal, bit = self.late_net_to_signal[left]
773773
other_src_loc = self.connect_src_loc[left]
774774
raise _ir.DriverConflict(f"Bit {bit} of signal {signal!r} has multiple drivers: "
775-
f"{other_src_loc} and {src_loc}")
775+
f"{other_src_loc[0]}:{other_src_loc[1]} and {src_loc[0]}:{src_loc[1]}")
776776
self.netlist.connections[left] = right
777777
self.connect_src_loc[left] = src_loc
778778

@@ -785,15 +785,15 @@ def emit_assign(self, module_idx: int, cd: "_cd.ClockDomain | None", lhs: _ast.V
785785
domain_name = cd.name if cd is not None else "comb"
786786
other_domain_name = driver.domain.name if driver.domain is not None else "comb"
787787
raise _ir.DriverConflict(
788-
f"Signal {lhs} driven from domain {domain_name} at {src_loc} and domain "
789-
f"{other_domain_name} at {driver.src_loc}")
788+
f"Signal {lhs!r} driven from domain {domain_name} at {src_loc[0]}:{src_loc[1]} and domain "
789+
f"{other_domain_name} at {driver.src_loc[0]}:{driver.src_loc[1]}")
790790
if driver.module_idx != module_idx:
791791
mod_name = ".".join(self.netlist.modules[module_idx].name or ("<toplevel>",))
792792
other_mod_name = \
793793
".".join(self.netlist.modules[driver.module_idx].name or ("<toplevel>",))
794794
raise _ir.DriverConflict(
795-
f"Signal {lhs} driven from module {mod_name} at {src_loc} and "
796-
f"module {other_mod_name} at {driver.src_loc}")
795+
f"Signal {lhs!r} driven from module {mod_name} at {src_loc[0]}:{src_loc[1]} and "
796+
f"module {other_mod_name} at {driver.src_loc[0]}:{driver.src_loc[1]}")
797797
else:
798798
driver = NetlistDriver(module_idx, lhs, domain=cd, src_loc=src_loc)
799799
self.drivers[lhs] = driver

tests/test_hdl_ast.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# amaranth: UnusedPrint=no, UnusedProperty
1+
# amaranth: UnusedPrint=no, UnusedProperty=no
22

33
import warnings
44
from enum import Enum, EnumMeta

tests/test_hdl_ir.py

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3142,3 +3142,40 @@ def test_assert(self):
31423142
(cell 21 0 (cover 0.6 20.0 neg 0.12 ('c')))
31433143
)
31443144
""")
3145+
3146+
class ConflictTestCase(FHDLTestCase):
3147+
def test_domain_conflict(self):
3148+
s = Signal()
3149+
m = Module()
3150+
m.d.sync += s.eq(1)
3151+
m1 = Module()
3152+
m1.d.comb += s.eq(2)
3153+
m.submodules.m1 = m1
3154+
with self.assertRaisesRegex(DriverConflict,
3155+
r"^Signal \(sig s\) driven from domain comb at "
3156+
r".*test_hdl_ir.py:\d+ and domain sync at "
3157+
r".*test_hdl_ir.py:\d+$"):
3158+
build_netlist(Fragment.get(m, None), [])
3159+
3160+
def test_module_conflict(self):
3161+
s = Signal()
3162+
m = Module()
3163+
m.d.sync += s.eq(1)
3164+
m1 = Module()
3165+
m1.d.sync += s.eq(2)
3166+
m.submodules.m1 = m1
3167+
with self.assertRaisesRegex(DriverConflict,
3168+
r"^Signal \(sig s\) driven from module top\.m1 at "
3169+
r".*test_hdl_ir.py:\d+ and module top at "
3170+
r".*test_hdl_ir.py:\d+$"):
3171+
build_netlist(Fragment.get(m, None), [])
3172+
3173+
def test_instance_conflict(self):
3174+
s = Signal()
3175+
m = Module()
3176+
m.d.sync += s.eq(1)
3177+
m.submodules.t = Instance("tt", o_s=s)
3178+
with self.assertRaisesRegex(DriverConflict,
3179+
r"^Bit 0 of signal \(sig s\) has multiple drivers: "
3180+
r".*test_hdl_ir.py:\d+ and .*test_hdl_ir.py:\d+$"):
3181+
build_netlist(Fragment.get(m, None), [])

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