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wanda-phiwhitequark
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lib.fifo: add Memory as submodules instead of its ports. [NFC]
This makes the generated netlist very slightly nicer.
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amaranth/lib/fifo.py

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -130,9 +130,9 @@ def elaborate(self, platform):
130130
do_read = self.r_rdy & self.r_en
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do_write = self.w_rdy & self.w_en
132132

133-
storage = Memory(width=self.width, depth=self.depth)
134-
w_port = m.submodules.w_port = storage.write_port()
135-
r_port = m.submodules.r_port = storage.read_port(domain="comb")
133+
storage = m.submodules.storage = Memory(width=self.width, depth=self.depth)
134+
w_port = storage.write_port()
135+
r_port = storage.read_port(domain="comb")
136136
produce = Signal(range(self.depth))
137137
consume = Signal(range(self.depth))
138138

@@ -257,7 +257,7 @@ def elaborate(self, platform):
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258258
do_inner_read = inner_r_rdy & (~self.r_rdy | self.r_en)
259259

260-
m.submodules.storage = storage = Memory(width=self.width, depth=inner_depth)
260+
storage = m.submodules.storage = Memory(width=self.width, depth=inner_depth)
261261
w_port = storage.write_port()
262262
r_port = storage.read_port(domain="sync", transparent=False)
263263
produce = Signal(range(inner_depth))
@@ -438,10 +438,9 @@ def elaborate(self, platform):
438438
m.d[self._w_domain] += self.w_level.eq(produce_w_bin - consume_w_bin)
439439
m.d.comb += self.r_level.eq(produce_r_bin - consume_r_bin)
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441-
storage = Memory(width=self.width, depth=self.depth)
442-
w_port = m.submodules.w_port = storage.write_port(domain=self._w_domain)
443-
r_port = m.submodules.r_port = storage.read_port (domain=self._r_domain,
444-
transparent=False)
441+
storage = m.submodules.storage = Memory(width=self.width, depth=self.depth)
442+
w_port = storage.write_port(domain=self._w_domain)
443+
r_port = storage.read_port (domain=self._r_domain, transparent=False)
445444
m.d.comb += [
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w_port.addr.eq(produce_w_bin[:-1]),
447446
w_port.data.eq(self.w_data),

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