@@ -130,9 +130,9 @@ def elaborate(self, platform):
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do_read = self .r_rdy & self .r_en
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do_write = self .w_rdy & self .w_en
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- storage = Memory (width = self .width , depth = self .depth )
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- w_port = m . submodules . w_port = storage .write_port ()
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- r_port = m . submodules . r_port = storage .read_port (domain = "comb" )
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+ storage = m . submodules . storage = Memory (width = self .width , depth = self .depth )
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+ w_port = storage .write_port ()
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+ r_port = storage .read_port (domain = "comb" )
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produce = Signal (range (self .depth ))
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consume = Signal (range (self .depth ))
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@@ -257,7 +257,7 @@ def elaborate(self, platform):
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do_inner_read = inner_r_rdy & (~ self .r_rdy | self .r_en )
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- m . submodules . storage = storage = Memory (width = self .width , depth = inner_depth )
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+ storage = m . submodules . storage = Memory (width = self .width , depth = inner_depth )
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w_port = storage .write_port ()
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r_port = storage .read_port (domain = "sync" , transparent = False )
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produce = Signal (range (inner_depth ))
@@ -438,10 +438,9 @@ def elaborate(self, platform):
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m .d [self ._w_domain ] += self .w_level .eq (produce_w_bin - consume_w_bin )
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m .d .comb += self .r_level .eq (produce_r_bin - consume_r_bin )
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- storage = Memory (width = self .width , depth = self .depth )
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- w_port = m .submodules .w_port = storage .write_port (domain = self ._w_domain )
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- r_port = m .submodules .r_port = storage .read_port (domain = self ._r_domain ,
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- transparent = False )
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+ storage = m .submodules .storage = Memory (width = self .width , depth = self .depth )
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+ w_port = storage .write_port (domain = self ._w_domain )
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+ r_port = storage .read_port (domain = self ._r_domain , transparent = False )
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m .d .comb += [
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w_port .addr .eq (produce_w_bin [:- 1 ]),
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w_port .data .eq (self .w_data ),
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