I'm a Senior Software Engineer and active open-source contributor specializing in RISC-V architecture, from bootloaders to operating systems and CI/CD automation.
💡 My work focuses on making the RISC-V ecosystem more accessible, testable, and production-ready by bridging low-level firmware with modern DevOps and cloud workflows.
🏠 Core Focus (Deep Work & Contributions)
- RISC-V Ecosystem → Application Porting, Open-source software contribution
- Bootloaders & OS Internals → U-Boot, OpenSBI, Linux kernel bring-up, device trees
- Firmware Porting → FreeRTOS on RISC-V microcontrollers, bare-metal development
⚡ Active Domains (Day-to-Day Engineering)
- CI/CD & Automation → GitHub Actions, GitLab CI, Jenkins, LAVA KernelCI
- Cloud & Infrastructure → Docker, Ansible, CloudFormation, Prometheus, Grafana
- Verification & RTL → SystemVerilog, Verilog, simulation/debug, test plan creation
🌱 Exploring & Expanding
- RISC-V ISA and upcoming extensions in new boards
- Automation at scale with open-source software
- Microkernel design and experimentation
📌 Cloud-V RISC-V CI Platform
A platform enabling the open-source community to get access to RISC-V boards.
📌 LAVA kernelCI port for Banana Pi F3 (Spacemit K1, RISC-V SoC)
- Added UART Y-modem boot support in SPL
- Modified bootflow to load U-Boot proper via UART and kernel/rootfs via NFS/TFTP
- Enabled CI integration with LAVA (Linaro Automation Validation Architecture)
- Blog and source code
- A RISC-V microkernel for validation of ISA according to the RISC-V privileged specification
📌 GitHub Actions runner port for RISC-V
- Patched the upstream source code of the GitHub Actions runner package to run on RISC-V with .NET version 8.0.101
- 📧 Email: alitariq4589@gmail.com
⭐️ “Pushing the boundaries of open-source software with open-source hardware.”