Binary encoding and operation codes

Binary encoding and operation codes are crucial in the interpretation and execution of instructions in the Virtual Processor's assembly language. This section provides an overview of the instruction encoding scheme and detailed opcode mappings for various operations.

Binary instruction encoding

Instruction encoding in the Virtual Processor involves specific binary fields:

• Op code (5 bits): Identifies the operation type.
• Input reg (3 bits): Specifies the involved register.
• Immediate data (8 bits): Used for immediate value instructions.
• Total size: Typically, each instruction is 16 bits.

Operation to opcode mapping

Each operation is assigned a unique opcode. The table below outlines these mappings:

Operation	Type	Op code	Suffix	Transformation
mov	act	0 0000	reg / imm val	Move data
goto	act	0 0001	imm val	Jump to ID
call	act	00010	imm val	Call subroutine
int	interrupt	0 0011	imm val	Check interrupt code
push	act	0 0100	reg	Push register to stack
pop	act	0 0110	reg	Pop from stack
div or /	act	0 0111	reg / imm val	Division operation
add or +	ope	0 1000	reg / imm val	Addition operation
sub or -	ope	0 1001	reg / imm val	Subtraction operation
mul or *	ope	0 1010	reg / imm val	Multiplication op.
rsh or >>	ope	0 1011	reg / imm val	Right shift operation
lsh or <<	ope	0 1100	reg / imm val	Left shift operation
and or &	ope	0 1101	reg / imm val	AND operation
or or |	ope	0 1110	reg / imm val	OR operation
not or !	ope	0 1111	reg / imm val	NOT operation
use_reg	act	1 0000	reg	Specify reg for next op
use_var	act	1 0001	imm val	Specify var for next op
lab	act	1 0010	imm val	Label operation
var	act	1 0011	imm val (var id)	Variable operation
mod or %	ope	1 0101	reg / imm val	Modulo operation
ret	act	1 0110	imm val	Return from subroutine
movfvar	act	1 0111	imm val (var id)	Move from var
movtvar	act	1 1000	imm val (var id)	Move to var
varsize	act	1 1001	imm val (var size)	Variable size
vardata	act	1 1010	imm val (data)	Variable data
...	...	...	...	...