I'm Ahmed Raza, SoC Design Verification Engineer at 10xEngineers, an Electrical Engineering graduate with majors in Computer Science from the University of Engineering and Technology, Lahore, Pakistan.

• Digital Logic Design
• Computer Architecture
• RISC-V
• Linux
• UVM (Universal Verification Methodology)
• SystemVerilog
• Constrained Random Verification
• Directed Testing
• Regression Testing
• Coverage-Driven Verification
• Functional Coverage
• Assertions
• Testbench Development
• UVM Testbench Components
• VIPs (Verification IP)
• Science Communication
• Project Management

• SoC Design Verification
• JTAG
• I3C
• Ethernet
• DDR (Double Data Rate)
• USB (Universal Serial Bus)

• Design Verification Engineer at 10xEngineers (Feb 2025 – Present)

  • Spearheading the verification of SoC components using Universal Verification Methodology (UVM) in a hybrid work environment.
  • Performing debugging, regression testing, and functional coverage closure for complex IPs like the AXI4-to-AHB-Lite Bridge.
  • Contributing to end-to-end IP verification cycles aligned with AMBA protocol standards.

• Associate Engineer at 10xEngineers (Jun 2024 – Feb 2025)

  • Specialized in SoC design verification, implementing layered SystemVerilog testbenches for protocols such as AHB3-Lite and AXI4.
  • Developed and integrated reusable UVM components including agents, drivers, and scoreboards, along with UVM RAL for register modeling.
  • Achieved full functional coverage through constrained-random testing and assertion-based verification.
  • Gained hands-on experience with RISC-V architecture and FPGA development via the RVfpga certification, working on C/Assembly programming and simulating designs on Verilator and Whisper ISS.
  • Verified key processor modules including the Ibex Core's Fetch Unit and Load Store Unit with advanced UVM testbenches.
  • Led critical projects such as:
    • AHB3-Lite Protocol Verification – Created a coverage-driven UVM environment with virtual sequences and protocol assertions.
    • AXI4-to-AHB-Lite Bridge Verification – Oversaw full-cycle verification, test planning, and performance validation.
    • RISC-V Peripheral Drivers – Designed and debugged GPIO, timers, and interrupts, with performance analysis on SweRV EH1 core.

• Chip Design Trainee Engineer at The Knowledge Streams x 10xEngineers (Jan 2024– June 2024)

  • Applied foundational principles of digital logic to develop and optimize chip design schematics.
  • Collaborated on projects focusing on the structural design of computer systems.
  • Engaged in the development and testing of RISC-V based systems.

• Science Communicator at Khwarizmi Science Society (July 2023– Present)

  • Creating engaging and informative content to bridge the gap between complex scientific concepts and the general audience.
  • Strategizing, organizing, and coordinating diverse science-related projects and events.
  • Compiling comprehensive reports and documentation on various scientific subjects.

• Data Mining & Business Intelligence Intern at NAVTTC (Jun 2023– Aug 2023)

  • Leveraged Python libraries to design and implement data mining solutions.
  • Utilized SQL and RDBMS to cleanse, transform, and merge data from diverse sources.
  • Conducted ad-hoc analysis to extract valuable insights from complex datasets and presented findings to stakeholders.

1. Verification of Generic Timer and Generic Counter ARM SSE500 Example

   • Developed UVM-based verification environments to validate the functionality and timing behavior of ARM SSE500 example modules.
   • Created test scenarios to verify counter rollover, interrupt triggering, and timer enable/disable sequences.
   • Achieved coverage closure with assertion-based checks and functional coverage metrics using SystemVerilog.
   • Debugged waveform outputs and register behavior to ensure compliance with expected operation under constrained-random stimuli.

2. UVM Based Verification of AXI to AHB Lite Bridge Vivado IP

• Completed verification process for a Vivado-generated AXI4-to-AHB-Lite Bridge IP.
• Designed layered UVM testbench with reusable components such as agents, sequencers, monitors, and scoreboards.
• Conducted regression testing, created functional coverage models, and ensured protocol compliance with AMBA specifications.

4. Air Quality Index (AQI) Monitoring through AI and IoT

   • Ignite funded final year project for cost-effective, real-time AQI monitoring.
   • Used Raspberry Pi to integrate sensors and transmitted information for prediction.
   • Applied LSTM and GRU machine learning algorithms for real-time prediction of AQI.

5. Line Following Robot

   • Led a team to develop a robot that follows a black line arena track.
   • Integrated sensors and motor drivers with TIVA TM4C123.

• BE Electrical Engineering, University of Engineering and Technology, Lahore (2019-2023)
  • Majors in Computer Science
  • Relevant Courses: Introduction to Computing (Python), Digital Systems Design, Computer Architecture, Very Large Scale Integration(VLSI), Microprocessor Systems, Programming Fundamental (C), Machine Learning (Python)

• Technical Skills: System Verilog, UVM, Constrained Random Verification, Coverage, Linux, Git, C, RISC-V Assembly, Spike
• Interests: SoC Design Verification, Computer Arch, Image Processing, Mathematics, Philosophy