GitHub - aexzhou/RISC-V-RV64I-CPU: A synthesizable RISC-V CPU with a 5-stage pipeline.

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A synthesizable RISC-V CPU with a 5-stage pipeline.

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Name		Name	Last commit message	Last commit date
Latest commit History 42 Commits
tests		tests
.gitignore		.gitignore
alu.sv		alu.sv
cpu.sv		cpu.sv
data.txt		data.txt
dataMem.sv		dataMem.sv
datapath.sv		datapath.sv
iMem.sv		iMem.sv
pipeline_tb.sv		pipeline_tb.sv
pipelinetest.txt		pipelinetest.txt
regfile.sv		regfile.sv
shifter.sv		shifter.sv
test_instructions_asm.txt		test_instructions_asm.txt