The MIPS architecture designed with verilog hardware modeling language.
This Processor was designed according to the MIPS specifications, supporting only a subset of the MIPS instructions. The processor is pipelined; However, hazards produced by executing several instructions in parrallel are not yet handled in the current version, but will be handled in subsequent versions.
- Add
- Sub
- Addi
- LW
- SW
- LH
- LHU
- AND
- OR
- SLL
- SLR
- OR
- BEQ
- SLT
- SLTU
- Data Memory: Stores the variables and the data of the program
- Instruction Memory: Stores the instrcuctions to be executed
- Multiplexers: Controls the data path.
- Control Unit: Outputs the control signals for the multiplexers and the ALU.
- SignExtend: Extends a 16 bit number to a 32 bit according to the appropriate sign.
- Adder.
- Program Counter: Register that stores the address of the current instruction.
- RegisterFile: Contains 32 Register for performing operations.
- shiftLeft2.
- ALU
- ALUControl: control signals that specifies the correct operation for the ALU.
- processor: The actual MIPS processor.
For detailed information about these instructions visit MIPS Instruction Reference
For this project it is highly recommended to use iverilog and vvp for compilation and simulation.
This section will explain how to build the processor and how to run a program on this MIPS processor.
First you will need to write a program in MIPS assembly that uses only the specified instructions. After writing the program you will need to assemble it to hexadecimal machine code. For examples: see the folders Mips and programs We suggest using MARS assembler. Now follow these instructions:
- Add the assembled hexedecimal file in the programs folder.
- Navigate your way to the tests folder and open Processor_tb.v file.
- Find the line where it says
$readmemh("program/file_name.bin", mips.IM.memory);
replace the file_name with the file name of your hexadecimal file.
Note: Almost any program can be written and executed using the provided instructiosn set.
make processor
iverilog -o processor *.v tests/Processor_tb.v
These commands should create the following file "processor"
Run the following command to begin the simulation:
vvp processor