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fix using wrong clock in speaker module
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hdl/sound/apple_speaker.sv

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,11 +13,11 @@ module apple_speaker (
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speaker_bit <= !speaker_bit;
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end
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16-
localparam COUNTDOWN_WIDTH = 24;
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localparam COUNTDOWN_WIDTH = 20;
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reg [COUNTDOWN_WIDTH - 1:0] countdown;
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reg prev_speaker_bit;
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20-
always_ff @(posedge a2bus_if.phi1_posedge) begin
20+
always_ff @(posedge a2bus_if.clk_logic) begin
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if (speaker_bit != prev_speaker_bit) begin
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countdown <= '1;
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end else begin

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