IIR filter

Author: edanuff

boards/a2n20v2/a2n20v2.gprj

@@ -33,10 +33,13 @@
         <File path="../../hdl/memory/a2mem_if.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/memory/apple_memory.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/mockingboard/mockingboard.sv" type="file.verilog" enable="1"/>
+        <File path="../../hdl/sound/apple_speaker.sv" type="file.verilog" enable="1"/>
+        <File path="../../hdl/sound/audio_out.v" type="file.verilog" enable="1"/>
         <File path="../../hdl/ssc/ssc_rom.vhd" type="file.vhdl" enable="1"/>
         <File path="../../hdl/ssc/super_serial_card.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/supersprite/supersprite.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/support/cdc.sv" type="file.verilog" enable="1"/>
+        <File path="../../hdl/support/iir_filter.v" type="file.verilog" enable="1"/>
         <File path="../../hdl/support/sdpram32.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/support/uart_6551.v" type="file.verilog" enable="1"/>
         <File path="../../hdl/support/uart_rx.v" type="file.verilog" enable="1"/>

boards/a2n20v2/hdl/top.sv

@@ -452,73 +452,60 @@ module top #(
 
     assign irq_n_w = (mb_irq_n && vdp_irq_n && ssc_irq_n) || !IRQ_OUT_ENABLE;
 
-    // HDMI
+    // Audio
+
+    wire speaker_audio_w;
+
+    apple_speaker apple_speaker (
+        .a2bus_if(a2bus_if),
+        .enable(APPLE_SPEAKER_ENABLE | sw_apple_speaker_w),
+        .speaker_o(speaker_audio_w)
+    );
+
+    localparam [31:0] aflt_rate = 7_056_000;
+    localparam [39:0] acx  = 4258969;
+    localparam  [7:0] acx0 = 3;
+    localparam  [7:0] acx1 = 3;
+    localparam  [7:0] acx2 = 1;
+    localparam [23:0] acy0 = -24'd6216759;
+    localparam [23:0] acy1 =  24'd6143386;
+    localparam [23:0] acy2 = -24'd2023767;
 
     localparam AUDIO_RATE = 44100;
     localparam AUDIO_BIT_WIDTH = 16;
-    localparam AUDIO_CLK_COUNT = (CLOCK_SPEED_HZ / 2) / AUDIO_RATE;
-    logic [$clog2(AUDIO_CLK_COUNT)-1:0] audio_counter_r;
-    logic clk_audio_r;
-
-    always_ff @(posedge clk_pixel_w)
-    begin
-        audio_counter_r <= (audio_counter_r == AUDIO_CLK_COUNT) ? 1'd0 : audio_counter_r + 1'd1;
-        clk_audio_r <= audio_counter_r == AUDIO_CLK_COUNT;
-    end
-
-    reg speaker_bit;
-    always @(posedge clk_logic_w or negedge system_reset_n_w) begin
-        if (!system_reset_n_w) begin
-            speaker_bit <= 1'b0;
-        end else if (phi1_posedge && (a2bus_if.addr[15:0] == 16'hC030) && !a2bus_if.m2sel_n) 
-            speaker_bit <= !speaker_bit;
-    end
+    wire clk_audio_w;
+    wire [15:0] audio_sample_word[1:0];
+    audio_out #(
+        .CLK_RATE(CLOCK_SPEED_HZ / 2),
+        .AUDIO_RATE(AUDIO_RATE)
+    ) audio_out
+    (
+        .reset(~device_reset_n_w),
+        .clk(clk_pixel_w),
+
+        .flt_rate(aflt_rate),
+        .cx(acx),
+        .cx0(acx0),
+        .cx1(acx1),
+        .cx2(acx2),
+        .cy0(acy0),
+        .cy1(acy1),
+        .cy2(acy2),
+
+        .is_signed(1'b0),
+        .core_l(ssp_audio_w + {mb_audio_l, 5'b00} + {speaker_audio_w, 13'b0}),
+        .core_r(ssp_audio_w + {mb_audio_r, 5'b00} + {speaker_audio_w, 13'b0}),
+
+        .audio_clk(clk_audio_w),
+        .audio_l(audio_sample_word[0]),
+        .audio_r(audio_sample_word[1])
+    );
 
-    // Apple intermal audio toggles a +5V signal to a speaker.  We cannot simply leave a square wave
-    // indefinitaley on the HDMI audio line, so we need to generate a pulse of a maximum length.
-    // If we don't do this, the HDMI audio line will essentially have an amplitude offset, which
-    // will cause the HDMI receiver to clip the audio or amplify anything such as the Mockingboard
-    // audio that is added to it.
-
-
-    reg [6:0] speaker_audio;
-    reg [7:0] speaker_audio_counter;
-    reg prev_speaker_bit;
-
-    always_ff @(posedge clk_pixel_w) begin
-        if (clk_audio_r) begin
-            if (speaker_bit != prev_speaker_bit) begin
-                speaker_audio_counter <= 8'd255;
-            end else begin
-                speaker_audio_counter <= speaker_audio_counter != 0 ? speaker_audio_counter - 8'd1 : 0;
-            end
-            prev_speaker_bit <= speaker_bit;
-
-            if ((speaker_audio_counter != 0) && (APPLE_SPEAKER_ENABLE | sw_apple_speaker_w)) begin
-                if (speaker_bit) begin
-                    speaker_audio <= speaker_audio != 7'd127 ? speaker_audio + 7'd1 : 7'd127;
-                end else begin
-                    speaker_audio <= speaker_audio != 7'd0 ? speaker_audio - 7'd1 : 7'd0;
-                end
-            end else begin
-                speaker_audio <= speaker_audio != 7'd0 ? speaker_audio - 7'd1 : 7'd0;
-            end
-        end
-    end
+    // HDMI
 
-    ////
     logic [2:0] tmds;
     wire tmdsClk;
 
-    //wire [15:0] sample = {ssp_psg_mix_audio_o, 2'b00};
-    reg [15:0] audio_sample_word[1:0], audio_sample_word0[1:0];
-    always @(posedge clk_pixel_w) begin  // crossing clock domain
-        audio_sample_word0[0] <= ssp_audio_w + {mb_audio_l, 4'b00} + {2'b0, speaker_audio, 7'b0};
-        audio_sample_word[0]  <= audio_sample_word0[0];
-        audio_sample_word0[1] <= ssp_audio_w + {mb_audio_r, 4'b00} + {2'b0, speaker_audio, 7'b0};
-        audio_sample_word[1]  <= audio_sample_word0[1];
-    end
-
     wire scanline_en = scanlines_w && hdmi_y[0];
 
     hdmi #(
@@ -536,7 +523,7 @@ module top #(
     ) hdmi (
         .clk_pixel_x5(clk_hdmi_w),
         .clk_pixel(clk_pixel_w),
-        .clk_audio(clk_audio_r),
+        .clk_audio(clk_audio_w),
         .rgb({
             scanline_en ? {1'b0, rgb_r_w[7:1]} : rgb_r_w,
             scanline_en ? {1'b0, rgb_g_w[7:1]} : rgb_g_w,

boards/a2n20v2/impl/pnr/a2n20v2.fs

@@ -62,7 +62,7 @@ <h1><a name="Message">Pin Messages</a></h1>
 </tr>
 <tr>
 <td class="label">Version</td>
-<td>V1.9.8.11 Education</td>
+<td>V1.9.9 Beta-4 Education</td>
 </tr>
 <tr>
 <td class="label">Part Number</td>
@@ -78,7 +78,7 @@ <h1><a name="Message">Pin Messages</a></h1>
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Tue Apr 23 22:38:30 2024
+<td>Thu Apr 25 15:18:35 2024
 </td>
 </tr>
 <tr>