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6 files changed

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‎boards/a2n20v2/impl/pnr/a2n20v2.fs

Lines changed: 1544 additions & 1544 deletions
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‎boards/a2n20v2/impl/pnr/a2n20v2.pin.html

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ <h1><a name="Message">Pin Messages</a></h1>
7878
</tr>
7979
<tr>
8080
<td class="label">Created Time</td>
81-
<td>Tue Apr 23 22:25:49 2024
81+
<td>Tue Apr 23 22:38:30 2024
8282
</td>
8383
</tr>
8484
<tr>

‎boards/a2n20v2/impl/pnr/a2n20v2.power.html

Lines changed: 53 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ <h1><a name="Message">Power Messages</a></h1>
8787
</tr>
8888
<tr>
8989
<td class="label">Created Time</td>
90-
<td>Tue Apr 23 22:25:49 2024
90+
<td>Tue Apr 23 22:38:30 2024
9191
</td>
9292
</tr>
9393
<tr>
@@ -100,15 +100,15 @@ <h2><a name="Power_Info">Power Information:</a></h2>
100100
<table class="summary_table">
101101
<tr>
102102
<td class="label">Total Power (mW)</td>
103-
<td>452.078</td>
103+
<td>452.098</td>
104104
</tr>
105105
<tr>
106106
<td class="label">Quiescent Power (mW)</td>
107107
<td>165.543</td>
108108
</tr>
109109
<tr>
110110
<td class="label">Dynamic Power (mW)</td>
111-
<td>286.535</td>
111+
<td>286.555</td>
112112
</tr>
113113
</table>
114114
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
@@ -192,9 +192,9 @@ <h2><a name="Supply_Summary">Supply Information:</a></h2>
192192
<tr>
193193
<td>VCC</td>
194194
<td>1.000</td>
195-
<td>275.668</td>
195+
<td>275.688</td>
196196
<td>102.887</td>
197-
<td>378.554</td>
197+
<td>378.574</td>
198198
</tr>
199199
<tr>
200200
<td>VCCX</td>
@@ -222,9 +222,9 @@ <h2><a name="By_Block_Type">Power By Block Type:</a></h2>
222222
</tr>
223223
<tr>
224224
<td>Logic</td>
225-
<td>5.028</td>
225+
<td>5.050</td>
226226
<td>NA</td>
227-
<td>5.567</td>
227+
<td>5.568</td>
228228
</tr>
229229
<tr>
230230
<td>IO</td>
@@ -248,7 +248,7 @@ <h2><a name="By_Block_Type">Power By Block Type:</a></h2>
248248
<td>DSP</td>
249249
<td>1.033
250250
<td>NA</td>
251-
<td>4.060
251+
<td>4.050
252252
</tr>
253253
</table>
254254
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
@@ -260,20 +260,20 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
260260
</tr>
261261
<tr>
262262
<td>top</td>
263-
<td>273.709</td>
264-
<td>273.709(273.324)</td>
263+
<td>273.731</td>
264+
<td>273.731(273.338)</td>
265265
<tr>
266266
<td>top/apple_bus/</td>
267-
<td>0.107</td>
268-
<td>0.107(0.000)</td>
267+
<td>0.104</td>
268+
<td>0.104(0.000)</td>
269269
<tr>
270270
<td>top/apple_memory/</td>
271-
<td>209.414</td>
272-
<td>209.414(209.326)</td>
271+
<td>209.416</td>
272+
<td>209.416(209.325)</td>
273273
<tr>
274274
<td>top/apple_memory/hires_aux_2000_5FFF/</td>
275-
<td>59.501</td>
276-
<td>59.501(0.000)</td>
275+
<td>59.500</td>
276+
<td>59.500(0.000)</td>
277277
<tr>
278278
<td>top/apple_memory/hires_aux_6000_9FFF/</td>
279279
<td>59.499</td>
@@ -305,23 +305,23 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
305305
<tr>
306306
<td>top/hdmi/</td>
307307
<td>0.499</td>
308-
<td>0.499(0.459)</td>
308+
<td>0.499(0.460)</td>
309309
<tr>
310310
<td>top/hdmi/tmds_gen[0].tmds_channel/</td>
311-
<td>0.053</td>
312-
<td>0.053(0.000)</td>
311+
<td>0.054</td>
312+
<td>0.054(0.000)</td>
313313
<tr>
314314
<td>top/hdmi/tmds_gen[1].tmds_channel/</td>
315-
<td>0.050</td>
316-
<td>0.050(0.000)</td>
315+
<td>0.052</td>
316+
<td>0.052(0.000)</td>
317317
<tr>
318318
<td>top/hdmi/tmds_gen[2].tmds_channel/</td>
319319
<td>0.051</td>
320320
<td>0.051(0.000)</td>
321321
<tr>
322322
<td>top/hdmi/true_hdmi_output.packet_assembler/</td>
323-
<td>0.109</td>
324-
<td>0.109(0.000)</td>
323+
<td>0.106</td>
324+
<td>0.106(0.000)</td>
325325
<tr>
326326
<td>top/hdmi/true_hdmi_output.packet_picker/</td>
327327
<td>0.196</td>
@@ -332,40 +332,40 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
332332
<td>0.048(0.000)</td>
333333
<tr>
334334
<td>top/mockingboard/</td>
335-
<td>1.057</td>
336-
<td>1.057(1.057)</td>
335+
<td>1.058</td>
336+
<td>1.058(1.058)</td>
337337
<tr>
338338
<td>top/mockingboard/m6522_left/</td>
339339
<td>0.194</td>
340340
<td>0.194(0.000)</td>
341341
<tr>
342342
<td>top/mockingboard/m6522_right/</td>
343-
<td>0.188</td>
344-
<td>0.188(0.000)</td>
343+
<td>0.189</td>
344+
<td>0.189(0.000)</td>
345345
<tr>
346346
<td>top/mockingboard/psg_left/</td>
347-
<td>0.337</td>
348-
<td>0.337(0.000)</td>
347+
<td>0.336</td>
348+
<td>0.336(0.000)</td>
349349
<tr>
350350
<td>top/mockingboard/psg_right/</td>
351-
<td>0.338</td>
352-
<td>0.338(0.000)</td>
351+
<td>0.339</td>
352+
<td>0.339(0.000)</td>
353353
<tr>
354354
<td>top/supersprite/</td>
355-
<td>41.538</td>
356-
<td>41.538(41.459)</td>
355+
<td>41.546</td>
356+
<td>41.546(41.467)</td>
357357
<tr>
358358
<td>top/supersprite/ssp_psg/</td>
359-
<td>0.336</td>
360-
<td>0.336(0.000)</td>
359+
<td>0.338</td>
360+
<td>0.338(0.000)</td>
361361
<tr>
362362
<td>top/supersprite/vdp/</td>
363-
<td>41.123</td>
364-
<td>41.123(41.123)</td>
363+
<td>41.128</td>
364+
<td>41.128(41.128)</td>
365365
<tr>
366366
<td>top/supersprite/vdp/f18a_core/</td>
367-
<td>41.123</td>
368-
<td>41.123(41.120)</td>
367+
<td>41.128</td>
368+
<td>41.128(41.126)</td>
369369
<tr>
370370
<td>top/supersprite/vdp/f18a_core/inst_color/</td>
371371
<td>0.036</td>
@@ -376,36 +376,36 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
376376
<td>0.062(0.000)</td>
377377
<tr>
378378
<td>top/supersprite/vdp/f18a_core/inst_cpu/</td>
379-
<td>0.596</td>
380-
<td>0.596(0.000)</td>
379+
<td>0.598</td>
380+
<td>0.598(0.000)</td>
381381
<tr>
382382
<td>top/supersprite/vdp/f18a_core/inst_sprites/</td>
383-
<td>8.545</td>
384-
<td>8.545(0.000)</td>
383+
<td>8.544</td>
384+
<td>8.544(0.000)</td>
385385
<tr>
386386
<td>top/supersprite/vdp/f18a_core/inst_tiles/</td>
387-
<td>2.175</td>
388-
<td>2.175(0.314)</td>
387+
<td>2.177</td>
388+
<td>2.177(0.314)</td>
389389
<tr>
390390
<td>top/supersprite/vdp/f18a_core/inst_tiles/inst_linebuf/</td>
391391
<td>0.314</td>
392392
<td>0.314(0.000)</td>
393393
<tr>
394394
<td>top/supersprite/vdp/f18a_core/inst_vga_cont/</td>
395-
<td>0.001</td>
396-
<td>0.001(0.000)</td>
395+
<td>0.002</td>
396+
<td>0.002(0.000)</td>
397397
<tr>
398398
<td>top/supersprite/vdp/f18a_core/inst_vram/</td>
399-
<td>29.705</td>
400-
<td>29.705(29.643)</td>
399+
<td>29.706</td>
400+
<td>29.706(29.643)</td>
401401
<tr>
402402
<td>top/supersprite/vdp/f18a_core/inst_vram/inst_ram/</td>
403403
<td>29.643</td>
404404
<td>29.643(0.000)</td>
405405
<tr>
406406
<td>top/vgc/</td>
407-
<td>0.070</td>
408-
<td>0.070(0.000)</td>
407+
<td>0.075</td>
408+
<td>0.075(0.000)</td>
409409
</table>
410410
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
411411
<table class="detail_table">
@@ -417,12 +417,12 @@ <h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
417417
<tr>
418418
<td>clk_logic</td>
419419
<td>54.000</td>
420-
<td>252.224</td>
420+
<td>252.242</td>
421421
</tr>
422422
<tr>
423423
<td>clk_pixel</td>
424424
<td>27.000</td>
425-
<td>15.859</td>
425+
<td>15.861</td>
426426
</tr>
427427
<tr>
428428
<td>NO CLOCK DOMAIN</td>

‎boards/a2n20v2/impl/pnr/a2n20v2.rpt.html

Lines changed: 15 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ <h1><a name="Message">PnR Messages</a></h1>
8383
</tr>
8484
<tr>
8585
<td class="label">Created Time</td>
86-
<td>Tue Apr 23 22:25:49 2024
86+
<td>Tue Apr 23 22:38:30 2024
8787
</td>
8888
</tr>
8989
<tr>
@@ -98,23 +98,23 @@ <h1><a name="PnR_Details">PnR Details</a></h1>
9898
<td class="label">Place & Route Process</td>
9999
<td>Running placement:
100100
Placement Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
101-
Placement Phase 1: CPU time = 0h 0m 0.372s, Elapsed time = 0h 0m 0.372s
101+
Placement Phase 1: CPU time = 0h 0m 0.347s, Elapsed time = 0h 0m 0.346s
102102
Placement Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
103103
Placement Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
104-
Total Placement: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
104+
Total Placement: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s
105105
Running routing:
106106
Routing Phase 0: CPU time = 0h 0m 0.004s, Elapsed time = 0h 0m 0.004s
107-
Routing Phase 1: CPU time = 0h 0m 0.444s, Elapsed time = 0h 0m 0.443s
107+
Routing Phase 1: CPU time = 0h 0m 0.446s, Elapsed time = 0h 0m 0.446s
108108
Routing Phase 2: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
109109
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
110-
Total Routing: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
110+
Total Routing: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s
111111
Generate output files:
112-
CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
112+
CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
113113
</td>
114114
</tr>
115115
<tr>
116116
<td class="label">Total Time and Memory Usage</td>
117-
<td>CPU time = 0h 0m 16s, Elapsed time = 0h 0m 16s, Peak memory usage = 424MB</td>
117+
<td>CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s, Peak memory usage = 424MB</td>
118118
</tr>
119119
</table>
120120
<br/>
@@ -129,12 +129,12 @@ <h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
129129
</tr>
130130
<tr>
131131
<td class="label">Logic</td>
132-
<td>6859/20736</td>
132+
<td>6889/20736</td>
133133
<td>34%</td>
134134
</tr>
135135
<tr>
136136
<td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
137-
<td>5989(5387 LUT, 602 ALU, 0 ROM16)</td>
137+
<td>6019(5415 LUT, 604 ALU, 0 ROM16)</td>
138138
<td>-</td>
139139
</tr>
140140
<tr>
@@ -144,7 +144,7 @@ <h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
144144
</tr>
145145
<tr>
146146
<td class="label">Register</td>
147-
<td>3143/15750</td>
147+
<td>3142/15750</td>
148148
<td>20%</td>
149149
</tr>
150150
<tr>
@@ -154,7 +154,7 @@ <h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
154154
</tr>
155155
<tr>
156156
<td class="label">&nbsp &nbsp --Logic Register as FF</td>
157-
<td>3124/15552</td>
157+
<td>3123/15552</td>
158158
<td>21%</td>
159159
</tr>
160160
<tr>
@@ -169,8 +169,8 @@ <h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
169169
</tr>
170170
<tr>
171171
<td class="label">CLS</td>
172-
<td>4775/10368</td>
173-
<td>47%</td>
172+
<td>4769/10368</td>
173+
<td>46%</td>
174174
</tr>
175175
<tr>
176176
<td class="label">I/O Port</td>
@@ -304,7 +304,7 @@ <h2><a name="Global_Clock_Usage_Summary">Global Clock Usage Summary:</a></h2>
304304
</tr>
305305
<tr>
306306
<td class="label">LW</td>
307-
<td>8/8(100%)</td>
307+
<td>7/8(88%)</td>
308308
</tr>
309309
<tr>
310310
<td class="label">GCLK_PIN</td>
@@ -347,7 +347,7 @@ <h2><a name="Global_Clock_Signals">Global Clock Signals:</a></h2>
347347
<td> TR TL BR BL</td>
348348
</tr>
349349
<tr>
350-
<td class="label">n992_7</td>
350+
<td class="label">n984_7</td>
351351
<td>LW</td>
352352
<td> -</td>
353353
</tr>
@@ -357,11 +357,6 @@ <h2><a name="Global_Clock_Signals">Global Clock Signals:</a></h2>
357357
<td> -</td>
358358
</tr>
359359
<tr>
360-
<td class="label">timer_a_count_15_7</td>
361-
<td>LW</td>
362-
<td> -</td>
363-
</tr>
364-
<tr>
365360
<td class="label">reset_n_r</td>
366361
<td>LW</td>
367362
<td> -</td>

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