Digital Verification Engineer
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PlanV
- Munich
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00:12
(UTC +02:00) - in/yilou-wang-a0569b215
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verilator/verilator
verilator/verilator PublicVerilator open-source SystemVerilog simulator and lint system
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planvtech/PlanV_Verilator_Feature_Tests
planvtech/PlanV_Verilator_Feature_Tests PublicPlanV CI System for testing Verilator-Features
SystemVerilog 1
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