๐ VLSI Design Engineer | MS in Electrical Engineering @ Purdue
๐ Specializing in RTL Design, FPGA Development & Digital System Architecture
๐ง Email | ๐ LinkedIn | ๐ Resume | ๐ United States
๐งญ Philosophy
"Designing tomorrowโs digital systems today โ one clock cycle at a time."
Iโm a passionate digital designer focused on building efficient, scalable, and synthesizable hardware systems. With a strong foundation in Verilog, FPGA development, and memory architecture, I love translating abstract logic into real-world digital hardware.
Whether itโs architecting FSMs, optimizing datapaths, or exploring memory systems, I enjoy solving problems that live at the intersection of elegant design and timing precision.
- โ RTL Design & Verification (Verilog, VHDL)
- โ FPGA-based System Implementation (Xilinx, Vivado)
- โ Memory Architecture & FIFO Buffers
- โ FSM Design & Control Logic
- โ SoC Integration & Embedded Digital Systems
Hardware Description Languages
Verilog โข VHDL โข SystemVerilog
Programming & Scripting
Python โข C โข C++ โข MATLAB โข Tcl/Tk
EDA Tools & Synthesis
Vivado โข Cadence Virtuoso โข Synopsys Design Compiler โข GTKWave โข Icarus Verilog โข Yosys
Design & Verification
RTL Design โข FSM Architecture โข Memory Systems โข Functional Verification โข Logic Synthesis
Protocols & Analysis
UART โข SPI โข I2C โข AXI โข STA โข CDC โข Power Optimization
Cross clock-domain FIFO with Gray code pointers & metastability prevention
- Dual-clock operation enabling safe data transfer between independent clock domains
- Gray code pointer synchronization with dual flip-flop synchronizers eliminating metastability
- Industry-standard CDC implementation with extra MSB for full/empty distinction
- Zero synthesis warnings with professional ModelSim simulation and Vivado synthesis verification
Parameterized memory buffer with pointer arithmetic & flag detection
- Full/empty status control with pointers
- Synthesizable design validated through comprehensive waveform analysis
- Post-synthesis schematic generation confirming zero-latch implementation
Sensor-based intelligent traffic management system
- Priority-based 5-state FSM with real-time traffic detection
- Parameterized timing control for scalable smart city deployment
- 100% synthesis success with deterministic state transitions
Complete SRAM collection: Single/Dual Port variants
- True dual-port enabling simultaneous independent R/W operations
- Parameterized depth/width for scalable memory solutions
- Comprehensive sync vs async read performance analysis
๐ฐ๏ธ UART Communication Protocol
Parameterized full-duplex UART with baud rate generator and FSM-based TX/RX logic
- Implements a modular UART system with transmitter, receiver, and configurable baud rate generator
- Supports full-duplex communication using separate FSMs for transmission and reception
- Includes 16x oversampling and loopback testing for accurate serial communication
- Validated using Icarus Verilog simulation and GTKWave waveform analysis
- Currently working on making the design work with FIFO (debugging errors)
High-performance multiplier with hybrid logic optimization
- 0.204 ns critical path delay @ 2 GHz, 62.47 ฮผW power dissipation
- Transmission gate + CMOS hybrid approach for speed/power balance
- Comprehensive comparison vs Wallace Tree & Booth architectures
Aug 2024 โ May 2025 | Indianapolis, IN
- Mentored student teams on AI/ML-based speech translation projects
- Supported cross-functional teams in building real-world engineering solutions
May 2024 โ Aug 2024 | Illinois, US
- Developed RTL designs for Marposs measurement system control functions
- Achieved 95% functional coverage through comprehensive verification testbenches
- Optimized electrical component integration reducing system setup time by 20%
Feb 2022 โ July 2023 | Mumbai, IN
- Led procurement and execution for major electrical engineering projects
- Maintained 100% execution success and high client satisfaction
June 2019 โ Jan 2022 | Mumbai, IN
- Delivered over 10 successful electrical design projects
- Improved on-site technical resolution by 10%
MS Electrical Engineering
Purdue University Indianapolis
Specialization: VLSI Design & FPGA Systems
- ๐ก Passionate about crafting efficient, synthesizable hardware that just works
- ๐ Continuously learning and mastering complex RTL design and verification techniques
- ๐ค Enjoy collaborating with cross-disciplinary teams to bring projects to life
- ๐ ๏ธ Experienced in bridging theoretical designs with practical FPGA implementations
- ๐ Always pushing boundaries by exploring new architectures and optimization methods