FreiTest Framework (Freiburg Test Suite)

This is a research framework for Automated Test Pattern Generation (ATPG). It contains components for fault list generation, circuit iteration, SAT gate encoding and fault simulation. This project does not have the aim to provide a full ATPG flow and lacks most features that are expected for production use (scan chain ordering, support for industrial file formats, integrated test bench validation, etc.).

Beware, that this framework is constantly being updated and extended for research. Some updates will break existing logic and no guarantee of compatibility is given. However, most updates require only minor changes.

On top of the FreiTest framework so-called workflows provide executable utilities for research, each designed for a specific purpose. All of the workflows are integrated into a single executable named freitest that handles command line parsing, configuration file processing and circuit loading.

Documentation

• First Steps
  • Git Setup
  • IDE Setup
  • Build Setup
  • Running FreiTest
  • Developing Applications
• Verilog Circuit Import
  • Cricuit Representation
  • Verilog Instantiator
  • Circuit Builder
  • Gate Library
• Automatic Test Pattern Generation (ATPG)
  • Solver Proxy
  • Logic Container
  • Logic Encoding
  • Logic Generator
  • Circuit Simulator
• Applications
  • Utility Applications
  • Circuit Applications
  • Scale4Edge Applications

Where is the code?

We are in the process of cleaning up the code, and removing and replacing proprietary data in our internal repository. We will upload the cleaned parts as soon as they are ready and the code will be available soon. Find the current progress below:

• Data / Cell-Libraries: Provide a generic cell-library verilog implementation to eliminate dependency on proprietary cell-libraries
• Data / Cell-Libraries: Provide a generic cell-library liberty file for synthesis
• Data / Benchmarks: Provide generated benchmarks for generic cell-library (through automatic generation)
• Data / Benchmarks: Provide ISCAS85, ISCAS89, ITC99, IWS05 benchmarks for generic cell-library (through automatic download and synthesis)
• Data / Benchmarks: Provide DarkRISCV and PicoRV32 processors for generic cell-library (through automatic download and synthesis)
• Data / Fault Models: Provide cell-aware fault model for generic cell-library
• Script: Generator for generic benchmark circuits and VCMs for generic cell-library
• Script: Synthesis for ISCAS85, ISCAS89, ITC99, IWS05 benchmarks for generic cell-library
• Script: Synthesis for DarkRISCV and PicoRV32 processors for generic cell-library
• Build: Clean build configuration from proprietary parts
• Build: Port Ubuntu 20.04 LTS Docker build to Ubuntu 24.04 LTS
• Build: Port CentOS 7 Docker build to CentOS 8 (for RHEL 8)
• Build: Finish Alpine linux Docker build
• Build: Provide GitHub CI configuration
• Code: Provide core FreiTest framework
• Code: Provide open-source basic ATPG workflows (Scale4Edge)
• Code: Provide open-source SBST ATPG workflows (Scale4Edge)
• Code: Provide open-source switching activity ATPG workflows (PoliTO)
• Code: Provide open-source untestability ATPG workflows (PoliTO)
• Code: Provide circuit export workflows
• Documentation: Provide core FreiTest framework
• Documentation: Provide open-source basic ATPG workflows (Scale4Edge)
• Documentation: Provide open-source SBST ATPG workflows (Scale4Edge)
• Documentation: Provide open-source switching activity ATPG workflows (PoliTO)
• Documentation: Provide open-source untestability ATPG workflows (PoliTO)
• Documentation: Provide circuit export workflows
• Configuration: Provide core FreiTest framework
• Configuration: Provide open-source basic ATPG workflows (Scale4Edge)
• Configuration: Provide open-source SBST ATPG workflows (Scale4Edge)
• Configuration: Provide open-source switching activity ATPG workflows (PoliTO)
• Configuration: Provide open-source untestability ATPG workflows (PoliTO)
• Configuration: Provide circuit export workflows

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This work is supported in part by the German Federal Ministry of Education and Research (BMBF) within the project Scale4Edge under contract no. 16ME0132.