// ensure read buffering logic is not generated for external components
external myreg_wide ext_reg1;
external regfile {
    myreg_wide reg1;
} ext_block;

ghdl -i --std=08  --workdir=sim_build --work=work ./regblock-vhdl-rtl/*.vhd ../interfaces/reg_utils.vhd && \
ghdl -m --std=08  --workdir=sim_build -Psim_build --work=work regblock_wrapper
./regblock-vhdl-rtl/regblock.vhd:1848:44:error: can't match slice with type STD_ULOGIC
    hwif_out.ext_block.addr <= decoded_addr(0 downto 0);
                                           ^
./regblock-vhdl-rtl/regblock.vhd:1962:74:error: no element "ext_reg1" in record type "field_storage_t"
                rbuf_storage.ext_reg1.data(15 downto 0) <= field_storage.ext_reg1.f1.value;
                                                                         ^
./regblock-vhdl-rtl/regblock.vhd:1968:43:error: selected element does not designate a record
            if decoded_reg_strb.ext_block.reg1(0) and not decoded_req_is_wr then
                                          ^
./regblock-vhdl-rtl/regblock.vhd:1969:80:error: no element "ext_block" in record type "field_storage_t"
                rbuf_storage.ext_block.reg1.data(15 downto 0) <= field_storage.ext_block.reg1.f1.value;
                                                                               ^