updated many missed references to systemverilog exporter

darsor · darsor · commit 8e833c16344f · 2025-04-30T14:20:34.000-06:00
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
@@ -1,4 +1,4 @@
-# Contributing to the PeakRDL-regblock code generator
+# Contributing to the PeakRDL-regblock-vhdl code generator
 We love your input! We want to make contributing to this project as easy and
 transparent as possible, whether it's:
 
@@ -9,13 +9,14 @@ transparent as possible, whether it's:
 - Becoming a maintainer
 
 
-## Open an issue using the [Issue Tracker](https://github.com/SystemRDL/PeakRDL-regblock/issues)
+## Open an issue using the [Issue Tracker](https://github.com/SystemRDL/PeakRDL-regblock-vhdl/issues)
 Talking to us is the easiest way to contribute! Report a bug or feature request by
-[opening a new issue](https://github.com/SystemRDL/PeakRDL-regblock/issues).
+[opening a new issue](https://github.com/SystemRDL/PeakRDL-regblock-vhdl/issues).
 
 Issue submission expectations:
 * Please keep each issue submission limited to one topic. This helps us stay organized.
 * Before opening an issue, check if one already exists for your topic. It may have already been discussed.
+    * Check the upstream SystemVerilog regblock exporter [issue tracker](https://github.com/SystemRDL/PeakRDL-regblock/issues) as well.
 * If submitting a bug, provide enough details so we can reproduce it on our end. (version number, example SystemRDL, etc...)
 * If submitting a feature request, please make sure ...
     * ... it does not violate the semantics of the SystemRDL standard.
diff --git a/docs/conf.py b/docs/conf.py
@@ -18,7 +18,7 @@
 
 # -- Project information -----------------------------------------------------
 
-project = 'PeakRDL-regblock'
+project = 'PeakRDL-regblock-vhdl'
 copyright = '%d, Alex Mykyta' % datetime.datetime.now().year
 author = 'Alex Mykyta'
 
diff --git a/docs/cpuif/apb.rst b/docs/cpuif/apb.rst
@@ -47,7 +47,7 @@ CPU interface.
 
 The APB4 CPU interface comes in two i/o port flavors:
 
-SystemVerilog Interface
+VHDL Record Interface
     * Command line: ``--cpuif apb4``
     * Interface Definition: :download:`apb4_intf_pkg.vhd <../../hdl-src/apb4_intf_pkg.vhd>`
     * Class: :class:`peakrdl_regblock_vhdl.cpuif.apb4.APB4_Cpuif`
diff --git a/docs/cpuif/customizing.rst b/docs/cpuif/customizing.rst
@@ -106,7 +106,7 @@ Via a package's entry point definition
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 If you are publishing a collection of PeakRDL plugins as an installable Python
 package, you can advertise them to PeakRDL using an entry point.
-This advertises your custom CPUIF class to the PeakRDL-regblock tool as a plugin
+This advertises your custom CPUIF class to the PeakRDL-regblock-vhdl tool as a plugin
 that should be loaded, and made available as a command-line option in PeakRDL.
 
 .. code-block:: toml
@@ -116,7 +116,7 @@ that should be loaded, and made available as a command-line option in PeakRDL.
 
 
 *   ``my_package``: The name of your installable Python module
-*   ``peakrdl-regblock-vhdl.cpuif``: This is the namespace that PeakRDL-regblock will
+*   ``peakrdl-regblock-vhdl.cpuif``: This is the namespace that PeakRDL-regblock-vhdl will
     search. Any cpuif plugins you create must be enclosed in this namespace in
     order to be discovered.
 *   ``my_package.my_module:MyCPUIF``: This is the import path that
diff --git a/docs/udps/extended_swacc.rst b/docs/udps/extended_swacc.rst
@@ -15,7 +15,7 @@ functionality.
 
 Properties
 ----------
-These UDP definitions, along with others supported by PeakRDL-regblock can be
+These UDP definitions, along with others supported by PeakRDL-regblock-vhdl can be
 enabled by compiling the following file along with your design:
 :download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
 
diff --git a/docs/udps/intro.rst b/docs/udps/intro.rst
@@ -5,7 +5,7 @@ Although the official SystemRDL spec defines numerous properties that allow you
 to define complex register map structures, sometimes they are not enough to
 accurately describe a necessary feature. Fortunately the SystemRDL spec allows
 the language to be extended using "User Defined Properties" (UDPs). The
-PeakRDL-regblock tool understands several UDPs that are described in this
+PeakRDL-regblock-vhdl tool understands several UDPs that are described in this
 section.
 
 To enable these UDPs, compile this RDL file prior to the rest of your design:
diff --git a/docs/udps/read_buffering.rst b/docs/udps/read_buffering.rst
@@ -27,7 +27,7 @@ properties:
 .. literalinclude:: ../../hdl-src/regblock_udps.rdl
     :lines: 10-18
 
-These UDP definitions, along with others supported by PeakRDL-regblock can be
+These UDP definitions, along with others supported by PeakRDL-regblock-vhdl can be
 enabled by compiling the following file along with your design:
 :download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
 
diff --git a/docs/udps/write_buffering.rst b/docs/udps/write_buffering.rst
@@ -33,7 +33,7 @@ properties:
 .. literalinclude:: ../../hdl-src/regblock_udps.rdl
     :lines: 20-28
 
-These UDP definitions, along with others supported by PeakRDL-regblock can be
+These UDP definitions, along with others supported by PeakRDL-regblock-vhdl can be
 enabled by compiling the following file along with your design:
 :download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
 
diff --git a/pyproject.toml b/pyproject.toml
@@ -45,7 +45,7 @@ cli = [
 Source = "https://github.com/SystemRDL/PeakRDL-regblock-vhdl"
 Tracker = "https://github.com/SystemRDL/PeakRDL-regblock-vhdl/issues"
 Changelog = "https://github.com/SystemRDL/PeakRDL-regblock-vhdl/releases"
-Documentation = "https://peakrdl-regblock.readthedocs.io/"
+Documentation = "https://peakrdl-regblock-vhdl.readthedocs.io/"
 
 [tool.setuptools.dynamic]
 version = {attr = "peakrdl_regblock_vhdl.__about__.__version__"}
diff --git a/src/peakrdl_regblock_vhdl/validate_design.py b/src/peakrdl_regblock_vhdl/validate_design.py
@@ -137,7 +137,7 @@ def enter_Field(self, node: 'FieldNode') -> None:
                     f"Software-writable field '{node.inst_name}' shall not span"
                     " multiple software-accessible subwords. Consider enabling"
                     " write double-buffering.\n"
-                    "For more details, see: https://peakrdl-regblock.readthedocs.io/en/latest/udps/write_buffering.html",
+                    "For more details, see: https://peakrdl-regblock-vhdl.readthedocs.io/en/latest/udps/write_buffering.html",
                     node.inst.inst_src_ref
                 )
 
@@ -149,7 +149,7 @@ def enter_Field(self, node: 'FieldNode') -> None:
                     " subwords and is modified on-read, making it impossible to"
                     " access its value correctly. Consider enabling read"
                     " double-buffering. \n"
-                    "For more details, see: https://peakrdl-regblock.readthedocs.io/en/latest/udps/read_buffering.html",
+                    "For more details, see: https://peakrdl-regblock-vhdl.readthedocs.io/en/latest/udps/read_buffering.html",
                     node.inst.inst_src_ref
                 )
 
diff --git a/tests/README.md b/tests/README.md
@@ -105,7 +105,7 @@ Each testcase group has its own folder and contains the following:
 : Empty file required for test discovery.
 
 `test_*/regblock.rdl`
-: Testcase RDL file. Testcase infrastructure will automatically compile this and generate the regblock output SystemVerilog.
+: Testcase RDL file. Testcase infrastructure will automatically compile this and generate the regblock output VHDL.
 
 `test_*/tb_template.sv`
 : Jinja template that defines the testcase-specific sequence.
