Single-bit std_logic to a slice (ghdl) (#28)

* peakrdl-regblock-vhdl used (0 => value) when assigning single-bit std_logic to a slice, instead of (low => value), causing “choice is out of index range” when low != 0

* Fix to use to_std_logic_vector instead of =>

Author: davekeeshan

src/peakrdl_regblock_vhdl/readback/generators.py

@@ -248,7 +248,7 @@ def process_buffered_reg_with_bypass(self, node: RegNode, regwidth: int, accessw
 
                 if field.width == 1:
                     # convert from std_logic to std_logic_vector
-                    value = f"(0 => {value})"
+                    value = f"to_std_logic_vector({value})"
                 self.add_content(f"readback_array({self.current_offset_str})({field.high} downto {field.low}) <= {value} when {rd_strb} else (others => '0');")
                 bidx = field.high + 1
 
@@ -317,7 +317,7 @@ def process_wide_reg(self, node: RegNode, accesswidth: int) -> None:
 
                     if field.width == 1:
                         # convert from std_logic to std_logic_vector
-                        value = f"(0 => {value})"
+                        value = f"to_std_logic_vector({value})"
                     self.add_content(f"readback_array({self.current_offset_str})({high} downto {low}) <= {value} when {rd_strb} else (others => '0');")
 
                     current_bit = field.high + 1