[pull] master from YosysHQ:master #372
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Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
The OCE signal in the SP(X)9B primitive is intended to control the
built-in output register. The documentation states that this port is
invalid when READ_MODE=0 is used. However, it has been experimentally
established that you cannot simply apply VCC or GND to it and forget it
- the discrepancy between the signal on this port and the signal on the
CE port leads to both skipping data reading and unnecessary reading
after CE has switched to 0.
Here we force these ports to be connected to the network, except in the
case where the user controls the OCE signal using non-constant signals.
Also:
* All PIPs for clock spines are made inaccessible to the common router
- in general, using these routes for signals that have not been
processed by a special globals router is fraught with effects that
are difficult to detect.
* The INV primitive has been added purely to speed up development -
this primitive is not generated by Yosys, but is almost always
present in vendor output files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
This type setting is not needed here - the packer distinguishes memory features by the X9 attribute, which will be correct anyway. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Ignore networks without users. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Don't stop at the first bad "arc", but use the global network to the maximum. * Report partial/full use of global wires for the network. * In case of complete routing failure, releasing the source - this is actually a BUGFIX. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Semi-dual port BSRAM (in Gowin terminology) has the same feature as Single Port - the CE and OCE signals must be synchronized. Such a sin has not yet been noticed for Dual Port. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
A small improvement - do not waste time analyzing already processed networks in the previous step (and possibly steps). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Corrects the situation when it is impossible to use IOBUF with two IOLOGIC elements at the same time - input and output. Addresses #1275 This is done by dividing one IOLOGIC Bel into two - input IOLOGIC and output IOLOGIC plus checking for compatibility of the cells located there. At the moment, this check is simple and allows only the combination of DDR and DDRC primitives. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
For the following primitives: - PADD9 - PADD18 - MULT9X9 - MULT18X18 - MULT36X36 - MULTALU18X18 - MULTALU36X18 - MULTADDALU18X18 - ALU54D packing and processing of fixed wires between macro and between DSP blocks is implemented. Clusters of DSP and macro blocks are processed using custom placement of cluster elements. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: gatecat <gatecat@ds0.me>
A segment router replaces the source-to-sink connection by general-purpose PIPs with bus-branch segment network connections. The problem arises when the source is connected to the sinks directly without switching as in the case of LUT->DFF, such wires should be left as is, which is what this PR does. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* route_clock: small cleanup * gatemate: include DDR route-throughs for clock router
* SER_CLK support * Update constids * wip * CLK_FEEDBACK * Handle SER_CLK and SER_CLK_N * clangformat * Cleanup * Use _ as separator for PLL CFGs * Remove unused clocking cells * Do not use same name for IO models * Fix IDDR merge * Cleanup * Properly handle user global signals * Move signal inversion in bitstream creation * Start adding multi die support * Display die location for pins used * Do not use constant s as locations * Cleanup SB_DRIVE handling * Use DDR locations from chip database * Place only in prefered die for now * Set D2D * Fixed typos
he good thing is that these cases are very few. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Fixes #1500 Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Fixes #1490 Signed-off-by: gatecat <gatecat@ds0.me>
Fixes #1263 Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Use loop enumeration of PIPs instead of direct name construction for the upper and lower ends of the segment wire. Also do not allow clock wires for segments. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: gatecat <gatecat@ds0.me>
* himbaechel: xilinx: replace `/usr/bin/pypy3` with `${Python3_EXECUTABLE}`
* himbaechel: xilinx: recognize `IMPORT_BBA_FILES` inside `CMakeLists.txt`
* himbaechel: xilinx: align CMake device selection behavior with gatemate
* CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
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