[pull] master from YosysHQ:master #372
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Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
…ome of the headers
…) and fixed an accidental copy problem
… and fixed an accidental copy problem
…memcpy()'ing into a non-POD type from the compiler There is still the possibility that this can explode horribly, but the result should be the same codegen and fixes the warning This also makes the helpers `inline` so they'll usually be compiled out for a nice speed boost
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Prohibits the use of Dynamic Clock Selection PIPs for networks where no DCS is present. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. BUGFIX Use a separate net for segment gates We use a temporary separate small network (typically 2 - 3 sinks) for routing from the segment network source to the segment gate. This fixes the rare but unpleasant case of self-intersection when a route to a gate is routed using PIPs after the gate, this is no longer allowed when using a separate small network. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> * Gowin. Fix style. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> --------- Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
* gatemate: implemented remaining PLL features * gatemate: allow longer carry chains
Each PLL output in ECP5 can be bypassed, which turns it into a wire that passes through ICLK unmodified. When an outputs mux is set to REFCLK, disregard other PLL configuration and copy the input constraint over unchanged.
* Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
Fill in the delays for PIP classes related to HCLK and IODELAY. Also: - if clock routing fails, we try to use the next fastest mechanism - segment networks; - fixing harmless typos. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: clock router Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> * Re-add clock router pip binding * Refactoring * Require globals to use a BUFG * Fix misunderstanding of GPIO/RAM clocking * Add plane info to chipdb * Force clock routing along a specific plane * Remove overly-limiting condition * Move clock router into its own file * Clock router based on delay * Refine clock router conditions * More detailed clock routing output * Clean up debug messages * clangformat --------- Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Also, convert paths to UTF-8 for Windows builds. See #1479.
* BRAM cascade mode support * Removed unused connections * Exclusive connection
Signed-off-by: gatecat <gatecat@ds0.me>
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