| Folder | Description |
|---|---|
| src | Projects for Sipeed Tang Primer 20K FPGA Dock Kit |
| README.md | This file |
| scr1test.gprj | File to open project in Gowin Eda |
Now the system on chip looks like this:
SCR1 is an open-source and free to use RISC-V compatible MCU-class core, designed and maintained by Syntacore. In this repository, I am porting the SCR 1 core to the Tang Primer 20K
As can be seen from the diagram, conceptually the Cis consists of two parts: SCR 1 cluster, which contains the SCR1 core itself, imem router, dmem router, tcm memory and timer.
This repository uses the scr1 microcontroller and fpga-sdk-prj sources.
The second part consists of a peripheral connected to the SCR1 cluster via the AHB bus. It consists of an asynchronous transceiver and read-only memory. The Read-only memory contains a uart program that implements a loopback from the uart back to the sender's com port.
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First you need to install the Gowin EDA.
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Then clone project and open scr1test.gprj file
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In opend project you need configure System Verilog version in "Project>Configure>Synthesize(General)". Select System Verilog 2017.
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Also you need configure Place and Route settings. Open "Project>Configure>Place and Route>Dual Purpose Pin", and select all points.
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Now you need run "synthesize" project and push on "place and route"
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Then you need to connect your Tang Primer 20K to PC through USB. On board you have two type-c connectors. You need one that is labeled usb-jtag. Before connecting the board to the computer, make sure that the first dip switch on the board is switched to the lower position, otherwise the sram will not be flashed.
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Open gowin programmer and flush sram.
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After flushing sram you can check, that program in ROM executes by processor. If you use Windows - open Putty. Select com port, where connected fpga and speed 9600. Then in line discipline optins select parameter "local echo" to "force on". After that you can open session, send characters to uart from COM port and see that characters are coming back on your com port from fpga.
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Loopback for UART is a test program. In the future, it is planned to install the sc-bl loader there.
