MIPS 32-Bit Processor (Verilog)

Problem Statement

Design a 5-stage pipelined RISC processor (with hazard detection and data forwarding units) capable of executing the following instructions:

0000 ADD   reg1, reg2, reg3
0004 NANDI reg4, reg1, CBED
0008 SUB   reg7, reg6, reg5
0012 LW    reg8, 5(reg7)
0016 NOR   reg10, reg8, reg9

Register File Initialization:

• reg2 = 10013
• reg3 = 01BA2
• reg5 = 234CF
• reg6 = 234CB
• reg9 = 54231

Instruction Format: The instruction format for this architecture is as follows:

31-28	27-24	23-20	19-16	15-0
OPCODE	Dest	Src1	Src2	Immediate

Instruction Encoding:

• Instruction 1: 0000
• Instruction 2: 0001
• Instruction 3: 0011
• Instruction 4: 0111
• Instruction 5: 1111

Processor Details:

• 16 registers (reg0 to reg15), each 32 bits wide
• Instruction memory: 32 bytes
• Data memory: as required by the program
• PC initialized to 0
• Register file: 2 read ports (RD1, RD2), 1 write port (WD)
• Read: At rising edge, RD1 and RD2 output data from RN1 and RN2
• Write: At falling edge, WD writes to WN if EnRW is true
• Instruction memory outputs 4 bytes at the positive clock edge if EnIM is high

Control Signals:

• ALUSrc: Selects second ALU input
• ALUOp (2 bits): ALU operation control
• MR: Read from memory
• MW: Write to memory
• MReg: Move data from memory to register
• EnIM: Enable instruction memory read
• EnRW: Enable register file write
• FA, FB: Forwarding mux controls
• IFIDWrite: Disable IF/ID change (hazard detection)
• PCWrite: Disable PC change (hazard detection)
• ST: Sets all control signals to zero (hazard detection)

Note: This processor is a custom/tweaked MIPS-like architecture for educational purposes. The instruction format, register file, and control signals are tailored to this project and may differ from standard MIPS implementations.

Introduction

This project implements a 32-bit MIPS processor using Verilog HDL. The design follows a classic 5-stage pipeline architecture, including modules for instruction fetch, decode, execute, memory access, and write-back. The processor supports basic arithmetic, logic, memory, and control operations, and is suitable for educational purposes and basic CPU architecture experiments.

Block Diagram

File Description

File Name	Brief Description
ALU.v	Arithmetic Logic Unit: Performs arithmetic and logic operations based on ALUop.
control.v	Control Unit: Generates control signals from opcode for pipeline stages.
Dmem.v	Data Memory: Implements data memory for load/store instructions.
EX.v	Execute Stage: Handles ALU operations and forwarding logic.
EX_MEM.v	EX/MEM Pipeline Register: Buffers signals/data between Execute and Memory stages.
fwd_unit.v	Forwarding Unit: Resolves data hazards by forwarding data between pipeline stages.
hazard_unit.v	Hazard Detection Unit: Detects and manages pipeline hazards (e.g., load-use).
ID.v	Instruction Decode: Decodes instructions, reads registers, and generates immediate values.
ID_EX.v	ID/EX Pipeline Register: Buffers signals/data between Decode and Execute stages.
IF_ID.v	IF/ID Pipeline Register: Buffers signals/data between Fetch and Decode stages.
IF_stage.v	Instruction Fetch: Handles program counter and instruction memory access.
imem.v	Instruction Memory: Stores and provides instructions to the processor.
MEM.v	Memory Stage: Interfaces with data memory for load/store operations.
MEM_WB.v	MEM/WB Pipeline Register: Buffers signals/data between Memory and Write-Back stages.
Regfile.v	Register File: Implements general-purpose registers for the processor.
top.v	Top-Level Module: Integrates all modules and connects pipeline stages.
WB.v	Write-Back Stage: Handles writing results back to the register file.
tb.v	Testbench: Simulates the processor, generates clock/reset, and observes outputs.

Overall Flow of the Project

1. Instruction Fetch (IF):
   • The program counter (PC) fetches instructions from imem.v.
   • Fetched instruction is passed to the IF/ID pipeline register.
2. Instruction Decode (ID):
   • Instruction is decoded in ID.v.
   • Register operands are read from Regfile.v.
   • Control signals are generated by control.v.
   • Immediate values are extracted and sign-extended.
   • Data is passed to the ID/EX pipeline register.
3. Execute (EX):
   • ALU operations are performed in ALU.v.
   • Forwarding and hazard detection handled by fwd_unit.v and hazard_unit.v.
   • Results and control signals are passed to the EX/MEM pipeline register.
4. Memory Access (MEM):
   • Data memory operations (load/store) are performed in Dmem.v via MEM.v.
   • Results are passed to the MEM/WB pipeline register.
5. Write-Back (WB):
   • Results are written back to the register file in WB.v.
   • The pipeline continues with the next instruction.

Simulation Waveforms

Paste your simulation waveform screenshots here to illustrate the processor's operation and verify correct execution.

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Additional Information

• How to Run:
  • Use the provided tb.v testbench for simulation in your preferred Verilog simulator (e.g., ModelSim, Vivado, Icarus Verilog).
  • Ensure all source files are included in the simulation project.
• Customization:
  • You can modify the instruction and data memory contents in imem.v and Dmem.v for custom test cases.
• Extending the Design:
  • Add more instructions, improve hazard handling, or implement advanced features (branch prediction, cache, etc.) as needed.

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For any questions or improvements, feel free to open an issue or contribute to this project.