Y86-64 Processor in Verilog

This repository contains an implementation of a Y86-64 processor built in Verilog. The Y86-64 architecture is a simplified version of x86-64, designed for educational purposes while maintaining key features such as instruction pipelining and memory operations.

Features:

• Fully functional Y86-64 ISA support
• Instruction fetch, decode, execute, memory, and write-back stages
• Hazard detection and forwarding mechanisms
• Memory and register file implementation
• Designed for simulation and testing in Verilog

This project serves as a foundation for exploring processor design, pipelining techniques, and computer architecture concepts.