GitHub - Shaheer-Ilyas2/RISC-V: This repository contains files for 3-stage RISC-V processor. The processor is designed using the System-Verilog and has been synthesized and tested on Questa Sim and Xilinx FPGA.

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This repository contains files for 3-stage RISC-V processor. The processor is designed using the System-Verilog and has been synthesized and tested on Questa Sim and Xilinx FPGA.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU.sv		ALU.sv
ALU_decoder.sv		ALU_decoder.sv
CSR_reg.sv		CSR_reg.sv
LS_unit.sv		LS_unit.sv
PC.sv		PC.sv
UartStates.vh		UartStates.vh
adder.sv		adder.sv
branch_cond.sv		branch_cond.sv
control_stage2.sv		control_stage2.sv
data_memory.sv		data_memory.sv
datapath.sv		datapath.sv
forwarding_unit.sv		forwarding_unit.sv
imem.txt		imem.txt
immediate_gen.sv		immediate_gen.sv
ins_mem.sv		ins_mem.sv
mux_2x1.sv		mux_2x1.sv
mux_3x1.sv		mux_3x1.sv
reg_file.sv		reg_file.sv
stage1_reg.sv		stage1_reg.sv
stage2_reg.sv		stage2_reg.sv
tb_datapath.sv		tb_datapath.sv
uart_transmiter.v		uart_transmiter.v

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This repository contains files for 3-stage RISC-V processor. The processor is designed using the System-Verilog and has been synthesized and tested on Questa Sim and Xilinx FPGA.