- 👋 Hi, I’m @SFCYang
- 👀 I’m interested in Microelectronics and Audio Electronics
- 🌱 I’m currently into ASIC and open source IC design tools
- 📫 How to reach me: s.castroyang@gmail.com
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@ UC
Popular repositories Loading
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camp_vlsi_2025
camp_vlsi_2025 PublicRepositorio para el campamento VLSI 2025 realizado en la Universidad Católica de Chile
Verilog 2
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8-bit-LFSR
8-bit-LFSR PublicDesigned a 8 bit Linear-Feedback Shift Register using OpenLane flow (RTL to GDS)
Verilog
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CSVCO-skywater130
CSVCO-skywater130 PublicCurrent Starved VCO design using opensource tools and skywater130nm
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sky130_ac3e_ip__cs_tes
sky130_ac3e_ip__cs_tes PublicForked from akiles-esta-usado/sky130_ac3e_ip__cs_tes
Makefile
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ttsky-verilog-template
ttsky-verilog-template Public templateForked from TinyTapeout/ttsky-verilog-template
Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
Verilog
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