Designed and implemented a 4-bit synchronous up counter using Verilog HDL, suitable for integration into digital systems requiring sequential counting operations such as timers, digital clocks, or address generation in memory systems.

🔧 Key Features: Synchronous Reset: Ensures the counter resets predictably on the rising clock edge.

Enable Signal: Allows conditional counting based on control logic.

Clocked Design: Operates on the positive edge of the input clock.

Overflow Handling: Automatically rolls over after reaching the maximum 4-bit value (4'b1111).

🧠 Technical Summary: Language: Verilog HDL

Simulation & Verification: Designed with testability in mind for simulation on tools like ModelSim, VCS, or QuestaSim.

Code Quality: Clean, synthesizable RTL following standard coding practices.

Reset Type: Synchronous Active-High Reset