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Merge tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux into clk-mtk
Pull MediaTek clk driver updates from Chen-Yu Tsai: A lot of clean up work, as well as new drivers and new functions - New clock drivers for MediaTek Helio X10 MT6795 - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion - Shrink MT8192 clock driver by deduplicating clock parent lists * tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux: (31 commits) clk: mediatek: mt8192: deduplicate parent clock lists clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*() clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes clk: mediatek: mt8183: Add clk mux notifier for MFG mux clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: add VDOSYS1 clock dt-bindings: clk: mediatek: Add MT8195 DPI clocks clk: mediatek: mt8192: add mtk_clk_simple_remove clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driver clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driver clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driver ...
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‎Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml

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@@ -23,6 +23,7 @@ properties:
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- mediatek,mt2701-infracfg
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- mediatek,mt2712-infracfg
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- mediatek,mt6765-infracfg
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- mediatek,mt6795-infracfg
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- mediatek,mt6779-infracfg_ao
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- mediatek,mt6797-infracfg
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- mediatek,mt7622-infracfg
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enum:
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- mediatek,mt2701-infracfg
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- mediatek,mt2712-infracfg
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- mediatek,mt6795-infracfg
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- mediatek,mt7622-infracfg
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- mediatek,mt7986-infracfg
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- mediatek,mt8135-infracfg

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

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- mediatek,mt2712-mmsys
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- mediatek,mt6765-mmsys
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- mediatek,mt6779-mmsys
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- mediatek,mt6795-mmsys
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- mediatek,mt6797-mmsys
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- mediatek,mt8167-mmsys
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- mediatek,mt8173-mmsys

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml

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- mediatek,mt2701-pericfg
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- mediatek,mt2712-pericfg
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- mediatek,mt6765-pericfg
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- mediatek,mt6795-pericfg
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- mediatek,mt7622-pericfg
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- mediatek,mt7629-pericfg
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- mediatek,mt8135-pericfg

‎Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml

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- mediatek,mt2712-apmixedsys
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- mediatek,mt6765-apmixedsys
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- mediatek,mt6779-apmixedsys
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- mediatek,mt6795-apmixedsys
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- mediatek,mt7629-apmixedsys
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- mediatek,mt8167-apmixedsys
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- mediatek,mt8183-apmixedsys

‎Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT6795
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maintainers:
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- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description: |
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The clock architecture in MediaTek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The devices provide clock gate control in different IP blocks.
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properties:
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compatible:
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enum:
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- mediatek,mt6795-mfgcfg
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- mediatek,mt6795-vdecsys
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- mediatek,mt6795-vencsys
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mfgcfg: clock-controller@13000000 {
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compatible = "mediatek,mt6795-mfgcfg";
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reg = <0 0x13000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: clock-controller@16000000 {
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compatible = "mediatek,mt6795-vdecsys";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vencsys: clock-controller@18000000 {
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compatible = "mediatek,mt6795-vencsys";
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reg = <0 0x18000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};

‎Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek System Clock Controller for MT6795
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maintainers:
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- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description:
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The Mediatek system clock controller provides various clocks and system
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configuration like reset and bus protection on MT6795.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt6795-apmixedsys
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- mediatek,mt6795-infracfg
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- mediatek,mt6795-pericfg
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- mediatek,mt6795-topckgen
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt6795-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};

‎Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml

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- mediatek,mt2712-topckgen
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- mediatek,mt6765-topckgen
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- mediatek,mt6779-topckgen
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- mediatek,mt6795-topckgen
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- mediatek,mt7629-topckgen
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- mediatek,mt7986-topckgen
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- mediatek,mt8167-topckgen

‎drivers/clk/mediatek/Kconfig

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@@ -259,6 +259,43 @@ config COMMON_CLK_MT6779_AUDSYS
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help
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This driver supports Mediatek MT6779 audsys clocks.
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config COMMON_CLK_MT6795
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tristate "Clock driver for MediaTek MT6795"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT6795 basic clocks and clocks
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required for various peripherals found on MediaTek.
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config COMMON_CLK_MT6795_MFGCFG
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tristate "Clock driver for MediaTek MT6795 mfgcfg"
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depends on COMMON_CLK_MT6795
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default COMMON_CLK_MT6795
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help
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This driver supports MediaTek MT6795 mfgcfg clocks.
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config COMMON_CLK_MT6795_MMSYS
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tristate "Clock driver for MediaTek MT6795 mmsys"
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depends on COMMON_CLK_MT6795
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default COMMON_CLK_MT6795
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help
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This driver supports MediaTek MT6795 mmsys clocks.
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config COMMON_CLK_MT6795_VDECSYS
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tristate "Clock driver for MediaTek MT6795 VDECSYS"
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depends on COMMON_CLK_MT6795
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default COMMON_CLK_MT6795
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help
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This driver supports MediaTek MT6795 vdecsys clocks.
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config COMMON_CLK_MT6795_VENCSYS
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tristate "Clock driver for MediaTek MT6795 VENCSYS"
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depends on COMMON_CLK_MT6795
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default COMMON_CLK_MT6795
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help
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This driver supports MediaTek MT6795 vencsys clocks.
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config COMMON_CLK_MT6797
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bool "Clock driver for MediaTek MT6797"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

‎drivers/clk/mediatek/Makefile

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@@ -17,6 +17,12 @@ obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
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obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
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obj-$(CONFIG_COMMON_CLK_MT6795) += clk-mt6795-apmixedsys.o clk-mt6795-infracfg.o \
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clk-mt6795-pericfg.o clk-mt6795-topckgen.o
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obj-$(CONFIG_COMMON_CLK_MT6795_MFGCFG) += clk-mt6795-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT6795_MMSYS) += clk-mt6795-mm.o
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obj-$(CONFIG_COMMON_CLK_MT6795_VDECSYS) += clk-mt6795-vdecsys.o
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obj-$(CONFIG_COMMON_CLK_MT6795_VENCSYS) += clk-mt6795-vencsys.o
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obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
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obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
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obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o

‎drivers/clk/mediatek/clk-apmixed.c

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@@ -70,7 +70,7 @@ static const struct clk_ops mtk_ref2usb_tx_ops = {
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.unprepare = mtk_ref2usb_tx_unprepare,
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};
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struct clk_hw * __init mtk_clk_register_ref2usb_tx(const char *name,
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struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name,
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const char *parent_name, void __iomem *reg)
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{
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struct mtk_ref2usb_tx *tx;
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return &tx->hw;
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}
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EXPORT_SYMBOL_GPL(mtk_clk_register_ref2usb_tx);
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void mtk_clk_unregister_ref2usb_tx(struct clk_hw *hw)
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{
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struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
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clk_hw_unregister(hw);
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kfree(tx);
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}
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EXPORT_SYMBOL_GPL(mtk_clk_unregister_ref2usb_tx);
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MODULE_LICENSE("GPL");

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