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clk: mediatek: mt8192: deduplicate parent clock lists
Some groups of clocks of the same type share the same list of parents. These lists were declared separately for each clock in older drivers, bloating the code. Merge some obvious duplicate parent clock lists in the MT8192 clock driver together to reduce the code size. These include: - apll_i2s*_m_parents into one as apll_i2s_m_parents - img1_parents & img2_parents into one as img_parents - msdc30_*_parents into one as msdc30_parents - camtg*_parents into cam_tg_parents - seninf*_parents into seninf_parents Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220926102523.2367530-6-wenst@chromium.org Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
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‎drivers/clk/mediatek/clk-mt8192.c

Lines changed: 25 additions & 181 deletions
Original file line numberDiff line numberDiff line change
@@ -167,22 +167,7 @@ static const char * const mdp_parents[] = {
167167
"mmpll_d5_d2"
168168
};
169169

170-
static const char * const img1_parents[] = {
171-
"clk26m",
172-
"univpll_d4",
173-
"tvdpll_ck",
174-
"mainpll_d4",
175-
"univpll_d5",
176-
"mmpll_d6",
177-
"univpll_d6",
178-
"mainpll_d6",
179-
"mmpll_d4_d2",
180-
"mainpll_d4_d2",
181-
"mmpll_d6_d2",
182-
"mmpll_d5_d2"
183-
};
184-
185-
static const char * const img2_parents[] = {
170+
static const char * const img_parents[] = {
186171
"clk26m",
187172
"univpll_d4",
188173
"tvdpll_ck",
@@ -280,61 +265,6 @@ static const char * const camtg_parents[] = {
280265
"univpll_192m_d32"
281266
};
282267

283-
static const char * const camtg2_parents[] = {
284-
"clk26m",
285-
"univpll_192m_d8",
286-
"univpll_d6_d8",
287-
"univpll_192m_d4",
288-
"univpll_d6_d16",
289-
"csw_f26m_d2",
290-
"univpll_192m_d16",
291-
"univpll_192m_d32"
292-
};
293-
294-
static const char * const camtg3_parents[] = {
295-
"clk26m",
296-
"univpll_192m_d8",
297-
"univpll_d6_d8",
298-
"univpll_192m_d4",
299-
"univpll_d6_d16",
300-
"csw_f26m_d2",
301-
"univpll_192m_d16",
302-
"univpll_192m_d32"
303-
};
304-
305-
static const char * const camtg4_parents[] = {
306-
"clk26m",
307-
"univpll_192m_d8",
308-
"univpll_d6_d8",
309-
"univpll_192m_d4",
310-
"univpll_d6_d16",
311-
"csw_f26m_d2",
312-
"univpll_192m_d16",
313-
"univpll_192m_d32"
314-
};
315-
316-
static const char * const camtg5_parents[] = {
317-
"clk26m",
318-
"univpll_192m_d8",
319-
"univpll_d6_d8",
320-
"univpll_192m_d4",
321-
"univpll_d6_d16",
322-
"csw_f26m_d2",
323-
"univpll_192m_d16",
324-
"univpll_192m_d32"
325-
};
326-
327-
static const char * const camtg6_parents[] = {
328-
"clk26m",
329-
"univpll_192m_d8",
330-
"univpll_d6_d8",
331-
"univpll_192m_d4",
332-
"univpll_d6_d16",
333-
"csw_f26m_d2",
334-
"univpll_192m_d16",
335-
"univpll_192m_d32"
336-
};
337-
338268
static const char * const uart_parents[] = {
339269
"clk26m",
340270
"univpll_d6_d8"
@@ -362,15 +292,7 @@ static const char * const msdc50_0_parents[] = {
362292
"univpll_d4_d2"
363293
};
364294

365-
static const char * const msdc30_1_parents[] = {
366-
"clk26m",
367-
"univpll_d6_d2",
368-
"mainpll_d6_d2",
369-
"mainpll_d7_d2",
370-
"msdcpll_d2"
371-
};
372-
373-
static const char * const msdc30_2_parents[] = {
295+
static const char * const msdc30_parents[] = {
374296
"clk26m",
375297
"univpll_d6_d2",
376298
"mainpll_d6_d2",
@@ -457,39 +379,6 @@ static const char * const seninf_parents[] = {
457379
"univpll_d5"
458380
};
459381

460-
static const char * const seninf1_parents[] = {
461-
"clk26m",
462-
"univpll_d4_d4",
463-
"univpll_d6_d2",
464-
"univpll_d4_d2",
465-
"univpll_d7",
466-
"univpll_d6",
467-
"mmpll_d6",
468-
"univpll_d5"
469-
};
470-
471-
static const char * const seninf2_parents[] = {
472-
"clk26m",
473-
"univpll_d4_d4",
474-
"univpll_d6_d2",
475-
"univpll_d4_d2",
476-
"univpll_d7",
477-
"univpll_d6",
478-
"mmpll_d6",
479-
"univpll_d5"
480-
};
481-
482-
static const char * const seninf3_parents[] = {
483-
"clk26m",
484-
"univpll_d4_d4",
485-
"univpll_d6_d2",
486-
"univpll_d4_d2",
487-
"univpll_d7",
488-
"univpll_d6",
489-
"mmpll_d6",
490-
"univpll_d5"
491-
};
492-
493382
static const char * const tl_parents[] = {
494383
"clk26m",
495384
"univpll_192m_d2",
@@ -649,52 +538,7 @@ static const char * const sflash_parents[] = {
649538
"univpll_d5_d8"
650539
};
651540

652-
static const char * const apll_i2s0_m_parents[] = {
653-
"aud_1_sel",
654-
"aud_2_sel"
655-
};
656-
657-
static const char * const apll_i2s1_m_parents[] = {
658-
"aud_1_sel",
659-
"aud_2_sel"
660-
};
661-
662-
static const char * const apll_i2s2_m_parents[] = {
663-
"aud_1_sel",
664-
"aud_2_sel"
665-
};
666-
667-
static const char * const apll_i2s3_m_parents[] = {
668-
"aud_1_sel",
669-
"aud_2_sel"
670-
};
671-
672-
static const char * const apll_i2s4_m_parents[] = {
673-
"aud_1_sel",
674-
"aud_2_sel"
675-
};
676-
677-
static const char * const apll_i2s5_m_parents[] = {
678-
"aud_1_sel",
679-
"aud_2_sel"
680-
};
681-
682-
static const char * const apll_i2s6_m_parents[] = {
683-
"aud_1_sel",
684-
"aud_2_sel"
685-
};
686-
687-
static const char * const apll_i2s7_m_parents[] = {
688-
"aud_1_sel",
689-
"aud_2_sel"
690-
};
691-
692-
static const char * const apll_i2s8_m_parents[] = {
693-
"aud_1_sel",
694-
"aud_2_sel"
695-
};
696-
697-
static const char * const apll_i2s9_m_parents[] = {
541+
static const char * const apll_i2s_m_parents[] = {
698542
"aud_1_sel",
699543
"aud_2_sel"
700544
};
@@ -724,9 +568,9 @@ static const struct mtk_mux top_mtk_muxes[] = {
724568
MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
725569
mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5),
726570
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
727-
img1_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
571+
img_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
728572
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
729-
img2_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
573+
img_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
730574
/* CLK_CFG_2 */
731575
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
732576
ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8),
@@ -747,16 +591,16 @@ static const struct mtk_mux top_mtk_muxes[] = {
747591
camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
748592
/* CLK_CFG_5 */
749593
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
750-
camtg2_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20),
594+
camtg_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20),
751595
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
752-
camtg3_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21),
596+
camtg_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21),
753597
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
754-
camtg4_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22),
598+
camtg_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22),
755599
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
756-
camtg5_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23),
600+
camtg_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23),
757601
/* CLK_CFG_6 */
758602
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel",
759-
camtg6_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24),
603+
camtg_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24),
760604
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
761605
uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
762606
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
@@ -767,9 +611,9 @@ static const struct mtk_mux top_mtk_muxes[] = {
767611
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
768612
msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28),
769613
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
770-
msdc30_1_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29),
614+
msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29),
771615
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
772-
msdc30_2_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30),
616+
msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30),
773617
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
774618
audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
775619
/* CLK_CFG_8 */
@@ -796,12 +640,12 @@ static const struct mtk_mux top_mtk_muxes[] = {
796640
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
797641
seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11),
798642
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
799-
seninf1_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12),
643+
seninf_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12),
800644
/* CLK_CFG_11 */
801645
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
802-
seninf2_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13),
646+
seninf_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13),
803647
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
804-
seninf3_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14),
648+
seninf_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14),
805649
MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel",
806650
tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15),
807651
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
@@ -847,16 +691,16 @@ static const struct mtk_mux top_mtk_muxes[] = {
847691

848692
static struct mtk_composite top_muxes[] = {
849693
/* CLK_AUDDIV_0 */
850-
MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s0_m_parents, 0x320, 16, 1),
851-
MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s1_m_parents, 0x320, 17, 1),
852-
MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s2_m_parents, 0x320, 18, 1),
853-
MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s3_m_parents, 0x320, 19, 1),
854-
MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s4_m_parents, 0x320, 20, 1),
855-
MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s5_m_parents, 0x320, 21, 1),
856-
MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s6_m_parents, 0x320, 22, 1),
857-
MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s7_m_parents, 0x320, 23, 1),
858-
MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s8_m_parents, 0x320, 24, 1),
859-
MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s9_m_parents, 0x320, 25, 1),
694+
MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s_m_parents, 0x320, 16, 1),
695+
MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s_m_parents, 0x320, 17, 1),
696+
MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s_m_parents, 0x320, 18, 1),
697+
MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s_m_parents, 0x320, 19, 1),
698+
MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s_m_parents, 0x320, 20, 1),
699+
MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s_m_parents, 0x320, 21, 1),
700+
MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s_m_parents, 0x320, 22, 1),
701+
MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320, 23, 1),
702+
MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320, 24, 1),
703+
MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320, 25, 1),
860704
};
861705

862706
static const struct mtk_composite top_adj_divs[] = {

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