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dmuszynsherbertx
dmuszyns
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herbertx
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crypto: qat - make ring to service map common for QAT GEN4
The function get_ring_to_svc_map() is present in both 420xx and 4xxx drivers. Rework the logic to make it generic to GEN4 devices and move it to qat_common/adf_gen4_hw_data.c. Signed-off-by: Damian Muszynski <damian.muszynski@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
1 parent a20a606 commit ed3d95f

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5 files changed

+90
-112
lines changed

5 files changed

+90
-112
lines changed

‎drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

Lines changed: 16 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -361,61 +361,6 @@ static u32 get_ena_thd_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
361361
}
362362
}
363363

364-
static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)
365-
{
366-
enum adf_cfg_service_type rps[RP_GROUP_COUNT] = { };
367-
const struct adf_fw_config *fw_config;
368-
u16 ring_to_svc_map;
369-
int i, j;
370-
371-
fw_config = get_fw_config(accel_dev);
372-
if (!fw_config)
373-
return 0;
374-
375-
/* If dcc, all rings handle compression requests */
376-
if (adf_get_service_enabled(accel_dev) == SVC_DCC) {
377-
for (i = 0; i < RP_GROUP_COUNT; i++)
378-
rps[i] = COMP;
379-
goto set_mask;
380-
}
381-
382-
for (i = 0; i < RP_GROUP_COUNT; i++) {
383-
switch (fw_config[i].ae_mask) {
384-
case ADF_AE_GROUP_0:
385-
j = RP_GROUP_0;
386-
break;
387-
case ADF_AE_GROUP_1:
388-
j = RP_GROUP_1;
389-
break;
390-
default:
391-
return 0;
392-
}
393-
394-
switch (fw_config[i].obj) {
395-
case ADF_FW_SYM_OBJ:
396-
rps[j] = SYM;
397-
break;
398-
case ADF_FW_ASYM_OBJ:
399-
rps[j] = ASYM;
400-
break;
401-
case ADF_FW_DC_OBJ:
402-
rps[j] = COMP;
403-
break;
404-
default:
405-
rps[j] = 0;
406-
break;
407-
}
408-
}
409-
410-
set_mask:
411-
ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT |
412-
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT |
413-
rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT |
414-
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT;
415-
416-
return ring_to_svc_map;
417-
}
418-
419364
static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num,
420365
const char * const fw_objs[], int num_objs)
421366
{
@@ -441,6 +386,20 @@ static const char *uof_get_name_420xx(struct adf_accel_dev *accel_dev, u32 obj_n
441386
return uof_get_name(accel_dev, obj_num, adf_420xx_fw_objs, num_fw_objs);
442387
}
443388

389+
static int uof_get_obj_type(struct adf_accel_dev *accel_dev, u32 obj_num)
390+
{
391+
const struct adf_fw_config *fw_config;
392+
393+
if (obj_num >= uof_get_num_objs(accel_dev))
394+
return -EINVAL;
395+
396+
fw_config = get_fw_config(accel_dev);
397+
if (!fw_config)
398+
return -EINVAL;
399+
400+
return fw_config[obj_num].obj;
401+
}
402+
444403
static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
445404
{
446405
const struct adf_fw_config *fw_config;
@@ -504,12 +463,13 @@ void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)
504463
hw_data->fw_mmp_name = ADF_420XX_MMP;
505464
hw_data->uof_get_name = uof_get_name_420xx;
506465
hw_data->uof_get_num_objs = uof_get_num_objs;
466+
hw_data->uof_get_obj_type = uof_get_obj_type;
507467
hw_data->uof_get_ae_mask = uof_get_ae_mask;
508468
hw_data->get_rp_group = get_rp_group;
509469
hw_data->get_ena_thd_mask = get_ena_thd_mask;
510470
hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;
511471
hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
512-
hw_data->get_ring_to_svc_map = get_ring_to_svc_map;
472+
hw_data->get_ring_to_svc_map = adf_gen4_get_ring_to_svc_map;
513473
hw_data->disable_iov = adf_disable_sriov;
514474
hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
515475
hw_data->enable_pm = adf_gen4_enable_pm;

‎drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

Lines changed: 16 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -320,61 +320,6 @@ static u32 get_ena_thd_mask_401xx(struct adf_accel_dev *accel_dev, u32 obj_num)
320320
}
321321
}
322322

323-
static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)
324-
{
325-
enum adf_cfg_service_type rps[RP_GROUP_COUNT];
326-
const struct adf_fw_config *fw_config;
327-
u16 ring_to_svc_map;
328-
int i, j;
329-
330-
fw_config = get_fw_config(accel_dev);
331-
if (!fw_config)
332-
return 0;
333-
334-
/* If dcc, all rings handle compression requests */
335-
if (adf_get_service_enabled(accel_dev) == SVC_DCC) {
336-
for (i = 0; i < RP_GROUP_COUNT; i++)
337-
rps[i] = COMP;
338-
goto set_mask;
339-
}
340-
341-
for (i = 0; i < RP_GROUP_COUNT; i++) {
342-
switch (fw_config[i].ae_mask) {
343-
case ADF_AE_GROUP_0:
344-
j = RP_GROUP_0;
345-
break;
346-
case ADF_AE_GROUP_1:
347-
j = RP_GROUP_1;
348-
break;
349-
default:
350-
return 0;
351-
}
352-
353-
switch (fw_config[i].obj) {
354-
case ADF_FW_SYM_OBJ:
355-
rps[j] = SYM;
356-
break;
357-
case ADF_FW_ASYM_OBJ:
358-
rps[j] = ASYM;
359-
break;
360-
case ADF_FW_DC_OBJ:
361-
rps[j] = COMP;
362-
break;
363-
default:
364-
rps[j] = 0;
365-
break;
366-
}
367-
}
368-
369-
set_mask:
370-
ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT |
371-
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT |
372-
rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT |
373-
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT;
374-
375-
return ring_to_svc_map;
376-
}
377-
378323
static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num,
379324
const char * const fw_objs[], int num_objs)
380325
{
@@ -407,6 +352,20 @@ static const char *uof_get_name_402xx(struct adf_accel_dev *accel_dev, u32 obj_n
407352
return uof_get_name(accel_dev, obj_num, adf_402xx_fw_objs, num_fw_objs);
408353
}
409354

355+
static int uof_get_obj_type(struct adf_accel_dev *accel_dev, u32 obj_num)
356+
{
357+
const struct adf_fw_config *fw_config;
358+
359+
if (obj_num >= uof_get_num_objs(accel_dev))
360+
return -EINVAL;
361+
362+
fw_config = get_fw_config(accel_dev);
363+
if (!fw_config)
364+
return -EINVAL;
365+
366+
return fw_config[obj_num].obj;
367+
}
368+
410369
static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
411370
{
412371
const struct adf_fw_config *fw_config;
@@ -487,11 +446,12 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)
487446
break;
488447
}
489448
hw_data->uof_get_num_objs = uof_get_num_objs;
449+
hw_data->uof_get_obj_type = uof_get_obj_type;
490450
hw_data->uof_get_ae_mask = uof_get_ae_mask;
491451
hw_data->get_rp_group = get_rp_group;
492452
hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;
493453
hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
494-
hw_data->get_ring_to_svc_map = get_ring_to_svc_map;
454+
hw_data->get_ring_to_svc_map = adf_gen4_get_ring_to_svc_map;
495455
hw_data->disable_iov = adf_disable_sriov;
496456
hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
497457
hw_data->enable_pm = adf_gen4_enable_pm;

‎drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -248,6 +248,7 @@ struct adf_hw_device_data {
248248
void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
249249
const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
250250
u32 (*uof_get_num_objs)(struct adf_accel_dev *accel_dev);
251+
int (*uof_get_obj_type)(struct adf_accel_dev *accel_dev, u32 obj_num);
251252
u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
252253
int (*get_rp_group)(struct adf_accel_dev *accel_dev, u32 ae_mask);
253254
u32 (*get_ena_thd_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);

‎drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
#include "adf_accel_devices.h"
55
#include "adf_cfg_services.h"
66
#include "adf_common_drv.h"
7+
#include "adf_fw_config.h"
78
#include "adf_gen4_hw_data.h"
89
#include "adf_gen4_pm.h"
910

@@ -433,3 +434,58 @@ int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev)
433434
return 0;
434435
}
435436
EXPORT_SYMBOL_GPL(adf_gen4_init_thd2arb_map);
437+
438+
u16 adf_gen4_get_ring_to_svc_map(struct adf_accel_dev *accel_dev)
439+
{
440+
struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
441+
enum adf_cfg_service_type rps[RP_GROUP_COUNT] = { };
442+
unsigned int ae_mask, start_id, worker_obj_cnt, i;
443+
u16 ring_to_svc_map;
444+
int rp_group;
445+
446+
if (!hw_data->get_rp_group || !hw_data->uof_get_ae_mask ||
447+
!hw_data->uof_get_obj_type || !hw_data->uof_get_num_objs)
448+
return 0;
449+
450+
/* If dcc, all rings handle compression requests */
451+
if (adf_get_service_enabled(accel_dev) == SVC_DCC) {
452+
for (i = 0; i < RP_GROUP_COUNT; i++)
453+
rps[i] = COMP;
454+
goto set_mask;
455+
}
456+
457+
worker_obj_cnt = hw_data->uof_get_num_objs(accel_dev) -
458+
ADF_GEN4_ADMIN_ACCELENGINES;
459+
start_id = worker_obj_cnt - RP_GROUP_COUNT;
460+
461+
for (i = start_id; i < worker_obj_cnt; i++) {
462+
ae_mask = hw_data->uof_get_ae_mask(accel_dev, i);
463+
rp_group = hw_data->get_rp_group(accel_dev, ae_mask);
464+
if (rp_group >= RP_GROUP_COUNT || rp_group < RP_GROUP_0)
465+
return 0;
466+
467+
switch (hw_data->uof_get_obj_type(accel_dev, i)) {
468+
case ADF_FW_SYM_OBJ:
469+
rps[rp_group] = SYM;
470+
break;
471+
case ADF_FW_ASYM_OBJ:
472+
rps[rp_group] = ASYM;
473+
break;
474+
case ADF_FW_DC_OBJ:
475+
rps[rp_group] = COMP;
476+
break;
477+
default:
478+
rps[rp_group] = 0;
479+
break;
480+
}
481+
}
482+
483+
set_mask:
484+
ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT |
485+
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT |
486+
rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT |
487+
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT;
488+
489+
return ring_to_svc_map;
490+
}
491+
EXPORT_SYMBOL_GPL(adf_gen4_get_ring_to_svc_map);

‎drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -235,5 +235,6 @@ int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number);
235235
void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev);
236236
void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
237237
int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev);
238+
u16 adf_gen4_get_ring_to_svc_map(struct adf_accel_dev *accel_dev);
238239

239240
#endif

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