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74 | 74 | #define PARF_INT_ALL_PLS_ERR BIT(15)
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75 | 75 | #define PARF_INT_ALL_PME_LEGACY BIT(16)
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76 | 76 | #define PARF_INT_ALL_PLS_PME BIT(17)
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| 77 | +#define PARF_INT_ALL_EDMA BIT(22) |
77 | 78 |
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78 | 79 | /* PARF_BDF_TO_SID_CFG register fields */
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79 | 80 | #define PARF_BDF_TO_SID_BYPASS BIT(0)
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@@ -395,7 +396,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
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395 | 396 | writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
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396 | 397 | val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
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397 | 398 | PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
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398 |
| - PARF_INT_ALL_LINK_UP; |
| 399 | + PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; |
399 | 400 | writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
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400 | 401 |
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401 | 402 | ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
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@@ -706,6 +707,7 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
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706 | 707 | .core_init_notifier = true,
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707 | 708 | .msi_capable = true,
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708 | 709 | .msix_capable = false,
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| 710 | + .align = SZ_4K, |
709 | 711 | };
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710 | 712 |
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711 | 713 | static const struct pci_epc_features *
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@@ -743,6 +745,7 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)
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743 | 745 | pcie_ep->pci.dev = dev;
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744 | 746 | pcie_ep->pci.ops = &pci_ops;
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745 | 747 | pcie_ep->pci.ep.ops = &pci_ep_ops;
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| 748 | + pcie_ep->pci.edma.nr_irqs = 1; |
746 | 749 | platform_set_drvdata(pdev, pcie_ep);
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747 | 750 |
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748 | 751 | ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
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