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dt-bindings: clock: samsung: remove define with number of clocks
Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Remove it entirely from the bindings, once Linux drivers stopped using them. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20230808082738.122804-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎include/dt-bindings/clock/exynos3250.h

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -256,12 +256,6 @@
256256
#define CLK_SCLK_UART2 248
257257
#define CLK_SCLK_MMC2 249
258258

259-
/*
260-
* Total number of clocks of main CMU.
261-
* NOTE: Must be equal to last clock ID increased by one.
262-
*/
263-
#define CLK_NR_CLKS 250
264-
265259
/*
266260
* CMU DMC
267261
*/
@@ -283,12 +277,6 @@
283277
#define CLK_DIV_DMCP 19
284278
#define CLK_DIV_DMCD 20
285279

286-
/*
287-
* Total number of clocks of main CMU.
288-
* NOTE: Must be equal to last clock ID increased by one.
289-
*/
290-
#define NR_CLKS_DMC 21
291-
292280
/*
293281
* CMU ISP
294282
*/
@@ -344,10 +332,4 @@
344332
#define CLK_ASYNCAXIM 46
345333
#define CLK_SCLK_MPWM_ISP 47
346334

347-
/*
348-
* Total number of clocks of CMU_ISP.
349-
* NOTE: Must be equal to last clock ID increased by one.
350-
*/
351-
#define NR_CLKS_ISP 48
352-
353335
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

‎include/dt-bindings/clock/exynos4.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -239,9 +239,6 @@
239239
#define CLK_DIV_GDR 460
240240
#define CLK_DIV_CORE2 461
241241

242-
/* must be greater than maximal clock id */
243-
#define CLK_NR_CLKS 462
244-
245242
/* Exynos4x12 ISP clocks */
246243
#define CLK_ISP_FIMC_ISP 1
247244
#define CLK_ISP_FIMC_DRC 2
@@ -275,6 +272,4 @@
275272
#define CLK_ISP_DIV_MCUISP0 29
276273
#define CLK_ISP_DIV_MCUISP1 30
277274

278-
#define CLK_NR_ISP_CLKS 31
279-
280275
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */

‎include/dt-bindings/clock/exynos5250.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,4 @@
177177
#define CLK_MOUT_MPLL 1029
178178
#define CLK_MOUT_VPLLSRC 1030
179179

180-
/* must be greater than maximal clock id */
181-
#define CLK_NR_CLKS 1031
182-
183180
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */

‎include/dt-bindings/clock/exynos5260-clk.h

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -137,8 +137,6 @@
137137
#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122
138138
#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123
139139
#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124
140-
#define TOP_NR_CLK 125
141-
142140

143141
/* List Of Clocks For CMU_EGL */
144142

@@ -153,8 +151,6 @@
153151
#define EGL_DOUT_ACLK_EGL 9
154152
#define EGL_DOUT_EGL2 10
155153
#define EGL_DOUT_EGL1 11
156-
#define EGL_NR_CLK 12
157-
158154

159155
/* List Of Clocks For CMU_KFC */
160156

@@ -168,8 +164,6 @@
168164
#define KFC_DOUT_KFC_ATCLK 8
169165
#define KFC_DOUT_KFC2 9
170166
#define KFC_DOUT_KFC1 10
171-
#define KFC_NR_CLK 11
172-
173167

174168
/* List Of Clocks For CMU_MIF */
175169

@@ -200,8 +194,6 @@
200194
#define MIF_CLK_INTMEM 25
201195
#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26
202196
#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27
203-
#define MIF_NR_CLK 28
204-
205197

206198
/* List Of Clocks For CMU_G3D */
207199

@@ -211,8 +203,6 @@
211203
#define G3D_DOUT_ACLK_G3D 4
212204
#define G3D_CLK_G3D_HPM 5
213205
#define G3D_CLK_G3D 6
214-
#define G3D_NR_CLK 7
215-
216206

217207
/* List Of Clocks For CMU_AUD */
218208

@@ -231,8 +221,6 @@
231221
#define AUD_SCLK_AUD_UART 13
232222
#define AUD_SCLK_PCM 14
233223
#define AUD_SCLK_I2S 15
234-
#define AUD_NR_CLK 16
235-
236224

237225
/* List Of Clocks For CMU_MFC */
238226

@@ -241,8 +229,6 @@
241229
#define MFC_CLK_MFC 3
242230
#define MFC_CLK_SMMU2_MFCM1 4
243231
#define MFC_CLK_SMMU2_MFCM0 5
244-
#define MFC_NR_CLK 6
245-
246232

247233
/* List Of Clocks For CMU_GSCL */
248234

@@ -272,8 +258,6 @@
272258
#define GSCL_CLK_SMMU3_MSCL1 24
273259
#define GSCL_SCLK_CSIS1_WRAP 25
274260
#define GSCL_SCLK_CSIS0_WRAP 26
275-
#define GSCL_NR_CLK 27
276-
277261

278262
/* List Of Clocks For CMU_FSYS */
279263

@@ -295,8 +279,6 @@
295279
#define FSYS_CLK_SMMU_RTIC 16
296280
#define FSYS_PHYCLK_USBDRD30 17
297281
#define FSYS_PHYCLK_USBHOST20 18
298-
#define FSYS_NR_CLK 19
299-
300282

301283
/* List Of Clocks For CMU_PERI */
302284

@@ -366,8 +348,6 @@
366348
#define PERI_SCLK_SPDIF 64
367349
#define PERI_SCLK_I2S 65
368350
#define PERI_SCLK_PCM1 66
369-
#define PERI_NR_CLK 67
370-
371351

372352
/* List Of Clocks For CMU_DISP */
373353

@@ -406,8 +386,6 @@
406386
#define DISP_CLK_DP 33
407387
#define DISP_SCLK_PIXEL 34
408388
#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35
409-
#define DISP_NR_CLK 36
410-
411389

412390
/* List Of Clocks For CMU_G2D */
413391

@@ -423,8 +401,6 @@
423401
#define G2D_CLK_SMMU_SSS 10
424402
#define G2D_CLK_SMMU_MDMA 11
425403
#define G2D_CLK_SMMU3_G2D 12
426-
#define G2D_NR_CLK 13
427-
428404

429405
/* List Of Clocks For CMU_ISP */
430406

@@ -461,6 +437,5 @@
461437
#define ISP_SCLK_SPI0_EXT 31
462438
#define ISP_SCLK_SPI1_EXT 32
463439
#define ISP_SCLK_UART_EXT 33
464-
#define ISP_NR_CLK 34
465440

466441
#endif

‎include/dt-bindings/clock/exynos5410.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,4 @@
6161
#define CLK_USBD301 367
6262
#define CLK_SSS 471
6363

64-
#define CLK_NR_CLKS 512
65-
6664
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */

‎include/dt-bindings/clock/exynos5420.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -271,7 +271,4 @@
271271
#define CLK_DOUT_PCLK_DREX0 798
272272
#define CLK_DOUT_PCLK_DREX1 799
273273

274-
/* must be greater than maximal clock id */
275-
#define CLK_NR_CLKS 800
276-
277274
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */

‎include/dt-bindings/clock/exynos5433.h

Lines changed: 0 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -188,8 +188,6 @@
188188
#define CLK_SCLK_ISP_SPI0_CAM1 252
189189
#define CLK_SCLK_HDMI_SPDIF_DISP 253
190190

191-
#define TOP_NR_CLK 254
192-
193191
/* CMU_CPIF */
194192
#define CLK_FOUT_MPHY_PLL 1
195193

@@ -200,8 +198,6 @@
200198
#define CLK_SCLK_MPHY_PLL 11
201199
#define CLK_SCLK_UFS_MPHY 11
202200

203-
#define CPIF_NR_CLK 12
204-
205201
/* CMU_MIF */
206202
#define CLK_FOUT_MEM0_PLL 1
207203
#define CLK_FOUT_MEM1_PLL 2
@@ -396,8 +392,6 @@
396392
#define CLK_SCLK_BUS_PLL_APOLLO 199
397393
#define CLK_SCLK_BUS_PLL_ATLAS 200
398394

399-
#define MIF_NR_CLK 201
400-
401395
/* CMU_PERIC */
402396
#define CLK_PCLK_SPI2 1
403397
#define CLK_PCLK_SPI1 2
@@ -468,8 +462,6 @@
468462
#define CLK_DIV_SCLK_SCI 70
469463
#define CLK_DIV_SCLK_SC_IN 71
470464

471-
#define PERIC_NR_CLK 72
472-
473465
/* CMU_PERIS */
474466
#define CLK_PCLK_HPM_APBIF 1
475467
#define CLK_PCLK_TMU1_APBIF 2
@@ -513,8 +505,6 @@
513505
#define CLK_SCLK_ANTIRBK_CNT 40
514506
#define CLK_SCLK_OTP_CON 41
515507

516-
#define PERIS_NR_CLK 42
517-
518508
/* CMU_FSYS */
519509
#define CLK_MOUT_ACLK_FSYS_200_USER 1
520510
#define CLK_MOUT_SCLK_MMC2_USER 2
@@ -621,8 +611,6 @@
621611
#define CLK_SCLK_USBDRD30 114
622612
#define CLK_PCIE 115
623613

624-
#define FSYS_NR_CLK 116
625-
626614
/* CMU_G2D */
627615
#define CLK_MUX_ACLK_G2D_266_USER 1
628616
#define CLK_MUX_ACLK_G2D_400_USER 2
@@ -653,8 +641,6 @@
653641
#define CLK_PCLK_G2D 25
654642
#define CLK_PCLK_SMMU_G2D 26
655643

656-
#define G2D_NR_CLK 27
657-
658644
/* CMU_DISP */
659645
#define CLK_FOUT_DISP_PLL 1
660646

@@ -771,8 +757,6 @@
771757
#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
772758
#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
773759

774-
#define DISP_NR_CLK 116
775-
776760
/* CMU_AUD */
777761
#define CLK_MOUT_AUD_PLL_USER 1
778762
#define CLK_MOUT_SCLK_AUD_PCM 2
@@ -824,8 +808,6 @@
824808
#define CLK_SCLK_I2S_BCLK 46
825809
#define CLK_SCLK_AUD_I2S 47
826810

827-
#define AUD_NR_CLK 48
828-
829811
/* CMU_BUS{0|1|2} */
830812
#define CLK_DIV_PCLK_BUS_133 1
831813

@@ -840,8 +822,6 @@
840822
#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
841823
#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
842824

843-
#define BUSx_NR_CLK 11
844-
845825
/* CMU_G3D */
846826
#define CLK_FOUT_G3D_PLL 1
847827

@@ -865,8 +845,6 @@
865845
#define CLK_PCLK_SYSREG_G3D 18
866846
#define CLK_SCLK_HPM_G3D 19
867847

868-
#define G3D_NR_CLK 20
869-
870848
/* CMU_GSCL */
871849
#define CLK_MOUT_ACLK_GSCL_111_USER 1
872850
#define CLK_MOUT_ACLK_GSCL_333_USER 2
@@ -898,8 +876,6 @@
898876
#define CLK_PCLK_SMMU_GSCL1 27
899877
#define CLK_PCLK_SMMU_GSCL2 28
900878

901-
#define GSCL_NR_CLK 29
902-
903879
/* CMU_APOLLO */
904880
#define CLK_FOUT_APOLLO_PLL 1
905881

@@ -935,8 +911,6 @@
935911
#define CLK_SCLK_HPM_APOLLO 29
936912
#define CLK_SCLK_APOLLO 30
937913

938-
#define APOLLO_NR_CLK 31
939-
940914
/* CMU_ATLAS */
941915
#define CLK_FOUT_ATLAS_PLL 1
942916

@@ -981,8 +955,6 @@
981955
#define CLK_ATCLK 38
982956
#define CLK_SCLK_ATLAS 39
983957

984-
#define ATLAS_NR_CLK 40
985-
986958
/* CMU_MSCL */
987959
#define CLK_MOUT_SCLK_JPEG_USER 1
988960
#define CLK_MOUT_ACLK_MSCL_400_USER 2
@@ -1016,8 +988,6 @@
1016988
#define CLK_PCLK_SMMU_JPEG 28
1017989
#define CLK_SCLK_JPEG 29
1018990

1019-
#define MSCL_NR_CLK 30
1020-
1021991
/* CMU_MFC */
1022992
#define CLK_MOUT_ACLK_MFC_400_USER 1
1023993

@@ -1040,8 +1010,6 @@
10401010
#define CLK_PCLK_SMMU_MFC_1 17
10411011
#define CLK_PCLK_SMMU_MFC_0 18
10421012

1043-
#define MFC_NR_CLK 19
1044-
10451013
/* CMU_HEVC */
10461014
#define CLK_MOUT_ACLK_HEVC_400_USER 1
10471015

@@ -1064,8 +1032,6 @@
10641032
#define CLK_PCLK_SMMU_HEVC_1 17
10651033
#define CLK_PCLK_SMMU_HEVC_0 18
10661034

1067-
#define HEVC_NR_CLK 19
1068-
10691035
/* CMU_ISP */
10701036
#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1
10711037
#define CLK_MOUT_ACLK_ISP_400_USER 2
@@ -1147,8 +1113,6 @@
11471113
#define CLK_SCLK_PIXELASYNCS_ISPC 76
11481114
#define CLK_SCLK_PIXELASYNCM_ISPC 77
11491115

1150-
#define ISP_NR_CLK 78
1151-
11521116
/* CMU_CAM0 */
11531117
#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1
11541118
#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2
@@ -1285,8 +1249,6 @@
12851249
#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132
12861250
#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133
12871251

1288-
#define CAM0_NR_CLK 134
1289-
12901252
/* CMU_CAM1 */
12911253
#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1
12921254

@@ -1404,12 +1366,8 @@
14041366
#define CLK_ATCLK_ISP 111
14051367
#define CLK_SCLK_ISP_CA5 112
14061368

1407-
#define CAM1_NR_CLK 113
1408-
14091369
/* CMU_IMEM */
14101370
#define CLK_ACLK_SLIMSSS 2
14111371
#define CLK_PCLK_SLIMSSS 35
14121372

1413-
#define IMEM_NR_CLK 36
1414-
14151373
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */

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