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clk: samsung: exynoautov9: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20230808082738.122804-11-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/clk/samsung/clk-exynosautov9.c

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,17 @@
1818
#include "clk.h"
1919
#include "clk-exynos-arm64.h"
2020

21+
/* NOTE: Must be equal to the last clock ID increased by one */
22+
#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1)
23+
#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
24+
#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
25+
#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
26+
#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
27+
#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
28+
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1)
29+
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1)
30+
#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1)
31+
2132
/* ---- CMU_TOP ------------------------------------------------------------ */
2233

2334
/* Register Offset definitions for CMU_TOP (0x1b240000) */
@@ -943,7 +954,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
943954
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
944955
.gate_clks = top_gate_clks,
945956
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
946-
.nr_clk_ids = TOP_NR_CLK,
957+
.nr_clk_ids = CLKS_NR_TOP,
947958
.clk_regs = top_clk_regs,
948959
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
949960
};
@@ -1003,7 +1014,7 @@ static const struct samsung_cmu_info busmc_cmu_info __initconst = {
10031014
.nr_div_clks = ARRAY_SIZE(busmc_div_clks),
10041015
.gate_clks = busmc_gate_clks,
10051016
.nr_gate_clks = ARRAY_SIZE(busmc_gate_clks),
1006-
.nr_clk_ids = BUSMC_NR_CLK,
1017+
.nr_clk_ids = CLKS_NR_BUSMC,
10071018
.clk_regs = busmc_clk_regs,
10081019
.nr_clk_regs = ARRAY_SIZE(busmc_clk_regs),
10091020
.clk_name = "dout_clkcmu_busmc_bus",
@@ -1061,7 +1072,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
10611072
.nr_div_clks = ARRAY_SIZE(core_div_clks),
10621073
.gate_clks = core_gate_clks,
10631074
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
1064-
.nr_clk_ids = CORE_NR_CLK,
1075+
.nr_clk_ids = CLKS_NR_CORE,
10651076
.clk_regs = core_clk_regs,
10661077
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
10671078
.clk_name = "dout_clkcmu_core_bus",
@@ -1301,7 +1312,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
13011312
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
13021313
.gate_clks = fsys0_gate_clks,
13031314
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
1304-
.nr_clk_ids = FSYS0_NR_CLK,
1315+
.nr_clk_ids = CLKS_NR_FSYS0,
13051316
.clk_regs = fsys0_clk_regs,
13061317
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
13071318
.clk_name = "dout_clkcmu_fsys0_bus",
@@ -1428,7 +1439,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
14281439
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
14291440
.gate_clks = fsys1_gate_clks,
14301441
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
1431-
.nr_clk_ids = FSYS1_NR_CLK,
1442+
.nr_clk_ids = CLKS_NR_FSYS1,
14321443
.clk_regs = fsys1_clk_regs,
14331444
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
14341445
.clk_name = "dout_clkcmu_fsys1_bus",
@@ -1495,7 +1506,7 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
14951506
.nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks),
14961507
.gate_clks = fsys2_gate_clks,
14971508
.nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks),
1498-
.nr_clk_ids = FSYS2_NR_CLK,
1509+
.nr_clk_ids = CLKS_NR_FSYS2,
14991510
.clk_regs = fsys2_clk_regs,
15001511
.nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs),
15011512
.clk_name = "dout_clkcmu_fsys2_bus",
@@ -1750,7 +1761,7 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
17501761
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
17511762
.gate_clks = peric0_gate_clks,
17521763
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
1753-
.nr_clk_ids = PERIC0_NR_CLK,
1764+
.nr_clk_ids = CLKS_NR_PERIC0,
17541765
.clk_regs = peric0_clk_regs,
17551766
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
17561767
.clk_name = "dout_clkcmu_peric0_bus",
@@ -2005,7 +2016,7 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
20052016
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
20062017
.gate_clks = peric1_gate_clks,
20072018
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
2008-
.nr_clk_ids = PERIC1_NR_CLK,
2019+
.nr_clk_ids = CLKS_NR_PERIC1,
20092020
.clk_regs = peric1_clk_regs,
20102021
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
20112022
.clk_name = "dout_clkcmu_peric1_bus",
@@ -2052,7 +2063,7 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = {
20522063
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
20532064
.gate_clks = peris_gate_clks,
20542065
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
2055-
.nr_clk_ids = PERIS_NR_CLK,
2066+
.nr_clk_ids = CLKS_NR_PERIS,
20562067
.clk_regs = peris_clk_regs,
20572068
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
20582069
.clk_name = "dout_clkcmu_peris_bus",

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