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clk: samsung: exynos850: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20230808082738.122804-10-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/clk/samsung/clk-exynos850.c

Lines changed: 24 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,19 @@
1717
#include "clk.h"
1818
#include "clk-exynos-arm64.h"
1919

20+
/* NOTE: Must be equal to the last clock ID increased by one */
21+
#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
22+
#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
23+
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
24+
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
25+
#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
26+
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
27+
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
28+
#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
29+
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
30+
#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1)
31+
#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
32+
2033
/* ---- CMU_TOP ------------------------------------------------------------- */
2134

2235
/* Register Offset definitions for CMU_TOP (0x120e0000) */
@@ -486,7 +499,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
486499
.nr_div_clks = ARRAY_SIZE(top_div_clks),
487500
.gate_clks = top_gate_clks,
488501
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
489-
.nr_clk_ids = TOP_NR_CLK,
502+
.nr_clk_ids = CLKS_NR_TOP,
490503
.clk_regs = top_clk_regs,
491504
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
492505
};
@@ -626,7 +639,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
626639
.nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
627640
.fixed_clks = apm_fixed_clks,
628641
.nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
629-
.nr_clk_ids = APM_NR_CLK,
642+
.nr_clk_ids = CLKS_NR_APM,
630643
.clk_regs = apm_clk_regs,
631644
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
632645
.clk_name = "dout_clkcmu_apm_bus",
@@ -909,7 +922,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
909922
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
910923
.fixed_clks = aud_fixed_clks,
911924
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
912-
.nr_clk_ids = AUD_NR_CLK,
925+
.nr_clk_ids = CLKS_NR_AUD,
913926
.clk_regs = aud_clk_regs,
914927
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
915928
.clk_name = "dout_aud",
@@ -1012,7 +1025,7 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
10121025
.nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
10131026
.fixed_clks = cmgp_fixed_clks,
10141027
.nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
1015-
.nr_clk_ids = CMGP_NR_CLK,
1028+
.nr_clk_ids = CLKS_NR_CMGP,
10161029
.clk_regs = cmgp_clk_regs,
10171030
.nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
10181031
.clk_name = "gout_clkcmu_cmgp_bus",
@@ -1108,7 +1121,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
11081121
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
11091122
.gate_clks = g3d_gate_clks,
11101123
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
1111-
.nr_clk_ids = G3D_NR_CLK,
1124+
.nr_clk_ids = CLKS_NR_G3D,
11121125
.clk_regs = g3d_clk_regs,
11131126
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
11141127
.clk_name = "dout_g3d_switch",
@@ -1210,7 +1223,7 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
12101223
.nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
12111224
.gate_clks = hsi_gate_clks,
12121225
.nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
1213-
.nr_clk_ids = HSI_NR_CLK,
1226+
.nr_clk_ids = CLKS_NR_HSI,
12141227
.clk_regs = hsi_clk_regs,
12151228
.nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
12161229
.clk_name = "dout_hsi_bus",
@@ -1342,7 +1355,7 @@ static const struct samsung_cmu_info is_cmu_info __initconst = {
13421355
.nr_div_clks = ARRAY_SIZE(is_div_clks),
13431356
.gate_clks = is_gate_clks,
13441357
.nr_gate_clks = ARRAY_SIZE(is_gate_clks),
1345-
.nr_clk_ids = IS_NR_CLK,
1358+
.nr_clk_ids = CLKS_NR_IS,
13461359
.clk_regs = is_clk_regs,
13471360
.nr_clk_regs = ARRAY_SIZE(is_clk_regs),
13481361
.clk_name = "dout_is_bus",
@@ -1451,7 +1464,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
14511464
.nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
14521465
.gate_clks = mfcmscl_gate_clks,
14531466
.nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
1454-
.nr_clk_ids = MFCMSCL_NR_CLK,
1467+
.nr_clk_ids = CLKS_NR_MFCMSCL,
14551468
.clk_regs = mfcmscl_clk_regs,
14561469
.nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
14571470
.clk_name = "dout_mfcmscl_mfc",
@@ -1626,7 +1639,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
16261639
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
16271640
.gate_clks = peri_gate_clks,
16281641
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
1629-
.nr_clk_ids = PERI_NR_CLK,
1642+
.nr_clk_ids = CLKS_NR_PERI,
16301643
.clk_regs = peri_clk_regs,
16311644
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
16321645
.clk_name = "dout_peri_bus",
@@ -1733,7 +1746,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
17331746
.nr_div_clks = ARRAY_SIZE(core_div_clks),
17341747
.gate_clks = core_gate_clks,
17351748
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
1736-
.nr_clk_ids = CORE_NR_CLK,
1749+
.nr_clk_ids = CLKS_NR_CORE,
17371750
.clk_regs = core_clk_regs,
17381751
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
17391752
.clk_name = "dout_core_bus",
@@ -1807,7 +1820,7 @@ static const struct samsung_cmu_info dpu_cmu_info __initconst = {
18071820
.nr_div_clks = ARRAY_SIZE(dpu_div_clks),
18081821
.gate_clks = dpu_gate_clks,
18091822
.nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
1810-
.nr_clk_ids = DPU_NR_CLK,
1823+
.nr_clk_ids = CLKS_NR_DPU,
18111824
.clk_regs = dpu_clk_regs,
18121825
.nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
18131826
.clk_name = "dout_dpu",

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