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SFxingyuwuConchuOD
SFxingyuwu
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ConchuOD
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clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
Add driver for the StarFive JH7110 Image-Signal-Process clock controller. And these clock controllers should power on and enable the clocks from SYSCRG before registering. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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‎drivers/clk/starfive/Kconfig

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@@ -56,3 +56,11 @@ config CLK_STARFIVE_JH7110_STG
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help
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Say yes here to support the System-Top-Group clock controller
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on the StarFive JH7110 SoC.
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config CLK_STARFIVE_JH7110_ISP
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tristate "StarFive JH7110 Image-Signal-Process clock support"
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depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU
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default m if ARCH_STARFIVE
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help
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Say yes here to support the Image-Signal-Process clock controller
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on the StarFive JH7110 SoC.

‎drivers/clk/starfive/Makefile

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@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o

‎drivers/clk/starfive/clk-starfive-jh7110-isp.c

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@@ -0,0 +1,232 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive JH7110 Image-Signal-Process Clock Driver
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*
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* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include "clk-starfive-jh7110.h"
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/* external clocks */
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#define JH7110_ISPCLK_ISP_TOP_CORE (JH7110_ISPCLK_END + 0)
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#define JH7110_ISPCLK_ISP_TOP_AXI (JH7110_ISPCLK_END + 1)
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#define JH7110_ISPCLK_NOC_BUS_ISP_AXI (JH7110_ISPCLK_END + 2)
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#define JH7110_ISPCLK_DVP_CLK (JH7110_ISPCLK_END + 3)
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#define JH7110_ISPCLK_EXT_END (JH7110_ISPCLK_END + 4)
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static struct clk_bulk_data jh7110_isp_top_clks[] = {
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{ .id = "isp_top_core" },
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{ .id = "isp_top_axi" }
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};
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static const struct jh71x0_clk_data jh7110_ispclk_data[] = {
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/* syscon */
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JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15,
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JH7110_ISPCLK_ISP_TOP_AXI),
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JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8,
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JH7110_ISPCLK_ISP_TOP_CORE),
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JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK),
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/* vin */
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JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16,
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JH7110_ISPCLK_ISP_TOP_CORE),
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JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16,
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JH7110_ISPCLK_ISP_TOP_CORE),
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JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60,
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JH7110_ISPCLK_ISP_TOP_CORE),
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JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0,
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JH7110_ISPCLK_DOM4_APB_FUNC),
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JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE),
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JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0,
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JH7110_ISPCLK_MIPI_RX0_PXL),
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JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0,
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JH7110_ISPCLK_MIPI_RX0_PXL),
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JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0,
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JH7110_ISPCLK_MIPI_RX0_PXL),
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JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
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JH7110_ISPCLK_MIPI_RX0_PXL),
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JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
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JH7110_ISPCLK_MIPI_RX0_PXL,
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JH7110_ISPCLK_DVP_INV),
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/* ispv2_top_wrapper */
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JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2,
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JH7110_ISPCLK_MIPI_RX0_PXL,
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JH7110_ISPCLK_DVP_INV),
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};
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static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv)
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{
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struct reset_control *top_rsts;
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/* The resets should be shared and other ISP modules will use its. */
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top_rsts = devm_reset_control_array_get_shared(priv->dev);
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if (IS_ERR(top_rsts))
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return dev_err_probe(priv->dev, PTR_ERR(top_rsts),
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"failed to get top resets\n");
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return reset_control_deassert(top_rsts);
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}
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static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data)
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{
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struct jh71x0_clk_priv *priv = data;
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unsigned int idx = clkspec->args[0];
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if (idx < JH7110_ISPCLK_END)
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return &priv->reg[idx].hw;
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return ERR_PTR(-EINVAL);
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}
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#ifdef CONFIG_PM
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static int jh7110_ispcrg_suspend(struct device *dev)
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{
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struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
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clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
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return 0;
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}
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static int jh7110_ispcrg_resume(struct device *dev)
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{
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struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
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return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
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}
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static const struct dev_pm_ops jh7110_ispcrg_pm_ops = {
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RUNTIME_PM_OPS(jh7110_ispcrg_suspend, jh7110_ispcrg_resume, NULL)
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};
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#endif
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static int jh7110_ispcrg_probe(struct platform_device *pdev)
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{
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struct jh71x0_clk_priv *priv;
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struct jh7110_top_sysclk *top;
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unsigned int idx;
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int ret;
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priv = devm_kzalloc(&pdev->dev,
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struct_size(priv, reg, JH7110_ISPCLK_END),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
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if (!top)
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return -ENOMEM;
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spin_lock_init(&priv->rmw_lock);
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priv->dev = &pdev->dev;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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top->top_clks = jh7110_isp_top_clks;
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top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks);
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ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
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if (ret)
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return dev_err_probe(priv->dev, ret, "failed to get main clocks\n");
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dev_set_drvdata(priv->dev, top);
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/* enable power domain and clocks */
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pm_runtime_enable(priv->dev);
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ret = pm_runtime_get_sync(priv->dev);
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if (ret < 0)
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return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
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ret = jh7110_isp_top_rst_init(priv);
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if (ret)
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goto err_exit;
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for (idx = 0; idx < JH7110_ISPCLK_END; idx++) {
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u32 max = jh7110_ispclk_data[idx].max;
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struct clk_parent_data parents[4] = {};
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struct clk_init_data init = {
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.name = jh7110_ispclk_data[idx].name,
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.ops = starfive_jh71x0_clk_ops(max),
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.parent_data = parents,
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.num_parents =
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((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
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.flags = jh7110_ispclk_data[idx].flags,
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};
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struct jh71x0_clk *clk = &priv->reg[idx];
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unsigned int i;
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const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = {
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"isp_top_core",
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"isp_top_axi",
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"noc_bus_isp_axi",
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"dvp_clk"
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};
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for (i = 0; i < init.num_parents; i++) {
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unsigned int pidx = jh7110_ispclk_data[idx].parents[i];
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if (pidx < JH7110_ISPCLK_END)
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parents[i].hw = &priv->reg[pidx].hw;
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else
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parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END];
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}
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clk->hw.init = &init;
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clk->idx = idx;
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clk->max_div = max & JH71X0_CLK_DIV_MASK;
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ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
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if (ret)
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goto err_exit;
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}
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ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_ispclk_get, priv);
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if (ret)
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goto err_exit;
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ret = jh7110_reset_controller_register(priv, "rst-isp", 3);
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if (ret)
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goto err_exit;
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return 0;
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err_exit:
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pm_runtime_put_sync(priv->dev);
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pm_runtime_disable(priv->dev);
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return ret;
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}
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static int jh7110_ispcrg_remove(struct platform_device *pdev)
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{
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static const struct of_device_id jh7110_ispcrg_match[] = {
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{ .compatible = "starfive,jh7110-ispcrg" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, jh7110_ispcrg_match);
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static struct platform_driver jh7110_ispcrg_driver = {
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.probe = jh7110_ispcrg_probe,
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.remove = jh7110_ispcrg_remove,
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.driver = {
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.name = "clk-starfive-jh7110-isp",
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.of_match_table = jh7110_ispcrg_match,
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.pm = pm_ptr(&jh7110_ispcrg_pm_ops),
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},
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};
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module_platform_driver(jh7110_ispcrg_driver);
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MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
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MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver");
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MODULE_LICENSE("GPL");

‎drivers/clk/starfive/clk-starfive-jh7110.h

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#include "clk-starfive-jh71x0.h"
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/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
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struct jh7110_top_sysclk {
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struct clk_bulk_data *top_clks;
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int top_clks_num;
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};
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int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
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const char *adev_name,
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u32 adev_id);

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