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clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
Add driver for the StarFive JH7110 System-Top-Group clock controller. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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‎drivers/clk/starfive/Kconfig

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@@ -48,3 +48,11 @@ config CLK_STARFIVE_JH7110_AON
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help
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Say yes here to support the always-on clock controller on the
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StarFive JH7110 SoC.
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config CLK_STARFIVE_JH7110_STG
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tristate "StarFive JH7110 System-Top-Group clock support"
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depends on CLK_STARFIVE_JH7110_SYS
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default m if ARCH_STARFIVE
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help
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Say yes here to support the System-Top-Group clock controller
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on the StarFive JH7110 SoC.

‎drivers/clk/starfive/Makefile

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@@ -7,3 +7,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o

‎drivers/clk/starfive/clk-starfive-jh7110-stg.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive JH7110 System-Top-Group Clock Driver
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*
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include "clk-starfive-jh7110.h"
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/* external clocks */
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#define JH7110_STGCLK_OSC (JH7110_STGCLK_END + 0)
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#define JH7110_STGCLK_HIFI4_CORE (JH7110_STGCLK_END + 1)
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#define JH7110_STGCLK_STG_AXIAHB (JH7110_STGCLK_END + 2)
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#define JH7110_STGCLK_USB_125M (JH7110_STGCLK_END + 3)
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#define JH7110_STGCLK_CPU_BUS (JH7110_STGCLK_END + 4)
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#define JH7110_STGCLK_HIFI4_AXI (JH7110_STGCLK_END + 5)
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#define JH7110_STGCLK_NOCSTG_BUS (JH7110_STGCLK_END + 6)
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#define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7)
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#define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8)
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static const struct jh71x0_clk_data jh7110_stgclk_data[] = {
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/* hifi4 */
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JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
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JH7110_STGCLK_HIFI4_CORE),
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/* usb */
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JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
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JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
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JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
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JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
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JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
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JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
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/* pci-e */
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JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
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JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
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JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
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JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
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JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
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JH7110_STGCLK_STG_AXIAHB),
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/* security */
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JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
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/* stg mtrx */
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JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
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JH7110_STGCLK_CPU_BUS),
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JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
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JH7110_STGCLK_NOCSTG_BUS),
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JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
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JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
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JH7110_STGCLK_CPU_BUS),
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JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
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JH7110_STGCLK_NOCSTG_BUS),
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JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
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JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
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JH7110_STGCLK_HIFI4_AXI),
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/* e24_rvpi */
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JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
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JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
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/* dw_sgdma1p */
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JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
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};
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static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data)
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{
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struct jh71x0_clk_priv *priv = data;
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unsigned int idx = clkspec->args[0];
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if (idx < JH7110_STGCLK_END)
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return &priv->reg[idx].hw;
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return ERR_PTR(-EINVAL);
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}
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static int jh7110_stgcrg_probe(struct platform_device *pdev)
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{
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struct jh71x0_clk_priv *priv;
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unsigned int idx;
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int ret;
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priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->rmw_lock);
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priv->dev = &pdev->dev;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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for (idx = 0; idx < JH7110_STGCLK_END; idx++) {
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u32 max = jh7110_stgclk_data[idx].max;
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struct clk_parent_data parents[4] = {};
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struct clk_init_data init = {
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.name = jh7110_stgclk_data[idx].name,
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.ops = starfive_jh71x0_clk_ops(max),
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.parent_data = parents,
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.num_parents =
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((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
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.flags = jh7110_stgclk_data[idx].flags,
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};
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struct jh71x0_clk *clk = &priv->reg[idx];
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const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = {
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"osc",
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"hifi4_core",
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"stg_axiahb",
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"usb_125m",
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"cpu_bus",
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"hifi4_axi",
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"nocstg_bus",
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"apb_bus"
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};
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unsigned int i;
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for (i = 0; i < init.num_parents; i++) {
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unsigned int pidx = jh7110_stgclk_data[idx].parents[i];
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if (pidx < JH7110_STGCLK_END)
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parents[i].hw = &priv->reg[pidx].hw;
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else if (pidx < JH7110_STGCLK_EXT_END)
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parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END];
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}
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clk->hw.init = &init;
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clk->idx = idx;
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clk->max_div = max & JH71X0_CLK_DIV_MASK;
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ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
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if (ret)
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return ret;
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}
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ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv);
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if (ret)
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return ret;
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return jh7110_reset_controller_register(priv, "rst-stg", 2);
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}
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static const struct of_device_id jh7110_stgcrg_match[] = {
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{ .compatible = "starfive,jh7110-stgcrg" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match);
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static struct platform_driver jh7110_stgcrg_driver = {
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.probe = jh7110_stgcrg_probe,
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.driver = {
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.name = "clk-starfive-jh7110-stg",
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.of_match_table = jh7110_stgcrg_match,
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},
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};
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module_platform_driver(jh7110_stgcrg_driver);
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MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
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MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
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MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver");
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MODULE_LICENSE("GPL");

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