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Daire McNamaraLorenzo Pieralisi
Daire McNamara
authored and
Lorenzo Pieralisi
committed
PCI: microchip: Align register, offset, and mask names with HW docs
Minor code re-organisation so that macros representing registers ascend in numerical order and use the same names as their hardware documentation. Removed registers not used by the driver. Link: https://lore.kernel.org/r/20230728131401.1615724-4-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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‎drivers/pci/controller/pcie-microchip-host.c

Lines changed: 60 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -30,66 +30,7 @@
3030
#define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
3131
#define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
3232

33-
/* PCIe Controller Phy Regs */
34-
#define SEC_ERROR_CNT 0x20
35-
#define DED_ERROR_CNT 0x24
36-
#define SEC_ERROR_INT 0x28
37-
#define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
38-
#define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
39-
#define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
40-
#define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
41-
#define NUM_SEC_ERROR_INTS (4)
42-
#define SEC_ERROR_INT_MASK 0x2c
43-
#define DED_ERROR_INT 0x30
44-
#define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
45-
#define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
46-
#define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
47-
#define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
48-
#define NUM_DED_ERROR_INTS (4)
49-
#define DED_ERROR_INT_MASK 0x34
50-
#define ECC_CONTROL 0x38
51-
#define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0)
52-
#define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
53-
#define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
54-
#define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3)
55-
#define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4)
56-
#define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5)
57-
#define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6)
58-
#define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7)
59-
#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8)
60-
#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9)
61-
#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10)
62-
#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11)
63-
#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12)
64-
#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13)
65-
#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14)
66-
#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15)
67-
#define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
68-
#define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
69-
#define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
70-
#define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
71-
#define LTSSM_STATE 0x5c
72-
#define LTSSM_L0_STATE 0x10
73-
#define PCIE_EVENT_INT 0x14c
74-
#define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
75-
#define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
76-
#define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
77-
#define PCIE_EVENT_INT_MASK GENMASK(2, 0)
78-
#define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
79-
#define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
80-
#define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
81-
#define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)
82-
#define PCIE_EVENT_INT_ENB_SHIFT 16
83-
#define NUM_PCIE_EVENTS (3)
84-
8533
/* PCIe Bridge Phy Regs */
86-
#define PCIE_PCI_IDS_DW1 0x9c
87-
88-
/* PCIe Config space MSI capability structure */
89-
#define MC_MSI_CAP_CTRL_OFFSET 0xe0u
90-
#define MC_MSI_MAX_Q_AVAIL (MC_NUM_MSI_IRQS_CODED << 1)
91-
#define MC_MSI_Q_SIZE (MC_NUM_MSI_IRQS_CODED << 4)
92-
9334
#define IMASK_LOCAL 0x180
9435
#define DMA_END_ENGINE_0_MASK 0x00000000u
9536
#define DMA_END_ENGINE_0_SHIFT 0
@@ -137,7 +78,8 @@
13778
#define ISTATUS_LOCAL 0x184
13879
#define IMASK_HOST 0x188
13980
#define ISTATUS_HOST 0x18c
140-
#define MSI_ADDR 0x190
81+
#define IMSI_ADDR 0x190
82+
#define MSI_ADDR 0x190
14183
#define ISTATUS_MSI 0x194
14284

14385
/* PCIe Master table init defines */
@@ -162,6 +104,62 @@
162104

163105
#define ATR_ENTRY_SIZE 32
164106

107+
/* PCIe Controller Phy Regs */
108+
#define SEC_ERROR_EVENT_CNT 0x20
109+
#define DED_ERROR_EVENT_CNT 0x24
110+
#define SEC_ERROR_INT 0x28
111+
#define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
112+
#define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
113+
#define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
114+
#define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
115+
#define NUM_SEC_ERROR_INTS (4)
116+
#define SEC_ERROR_INT_MASK 0x2c
117+
#define DED_ERROR_INT 0x30
118+
#define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
119+
#define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
120+
#define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
121+
#define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
122+
#define NUM_DED_ERROR_INTS (4)
123+
#define DED_ERROR_INT_MASK 0x34
124+
#define ECC_CONTROL 0x38
125+
#define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0)
126+
#define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
127+
#define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
128+
#define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3)
129+
#define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4)
130+
#define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5)
131+
#define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6)
132+
#define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7)
133+
#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8)
134+
#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9)
135+
#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10)
136+
#define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11)
137+
#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12)
138+
#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13)
139+
#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14)
140+
#define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15)
141+
#define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
142+
#define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
143+
#define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
144+
#define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
145+
#define PCIE_EVENT_INT 0x14c
146+
#define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
147+
#define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
148+
#define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
149+
#define PCIE_EVENT_INT_MASK GENMASK(2, 0)
150+
#define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
151+
#define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
152+
#define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
153+
#define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)
154+
#define PCIE_EVENT_INT_ENB_SHIFT 16
155+
#define NUM_PCIE_EVENTS (3)
156+
157+
/* PCIe Config space MSI capability structure */
158+
#define MC_MSI_CAP_CTRL_OFFSET 0xe0u
159+
#define MC_MSI_MAX_Q_AVAIL (MC_NUM_MSI_IRQS_CODED << 1)
160+
#define MC_MSI_Q_SIZE (MC_NUM_MSI_IRQS_CODED << 4)
161+
162+
/* Events */
165163
#define EVENT_PCIE_L2_EXIT 0
166164
#define EVENT_PCIE_HOTRST_EXIT 1
167165
#define EVENT_PCIE_DLUP_EXIT 2
@@ -1086,15 +1084,15 @@ static int mc_platform_init(struct pci_config_window *cfg)
10861084
SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;
10871085
writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT);
10881086
writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK);
1089-
writel_relaxed(0, ctrl_base_addr + SEC_ERROR_CNT);
1087+
writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT);
10901088

10911089
val = DED_ERROR_INT_TX_RAM_DED_ERR_INT |
10921090
DED_ERROR_INT_RX_RAM_DED_ERR_INT |
10931091
DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT |
10941092
DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;
10951093
writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT);
10961094
writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK);
1097-
writel_relaxed(0, ctrl_base_addr + DED_ERROR_CNT);
1095+
writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT);
10981096

10991097
writel_relaxed(0, bridge_base_addr + IMASK_HOST);
11001098
writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);

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