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Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and 'clk-lmk' into clk-next
 - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Remove non-OF mmp clk drivers - Move number of clks from DT headers to drivers * clk-imx: clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz clk: imx: pll14xx: align pdiv with reference manual clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op clk: imx25: make __mx25_clocks_init return void clk: imx25: print silicon revision during init dt-bindings: clocks: imx8mp: make sai4 a dummy clock clk: imx8mp: fix sai4 clock clk: imx: imx8ulp: update SPLL2 type clk: imx: pllv4: Fix SPLL2 MULT range clk: imx: imx8: add audio clock mux driver dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() clk: imx: clk-gpr-mux: Simplify .determine_rate() clk: imx: Add 519.75MHz frequency support for imx9 pll clk: imx93: Add PDM IPG clk dt-bindings: clock: imx93: Add PDM IPG clk * clk-samsung: dt-bindings: clock: samsung: remove define with number of clocks clk: samsung: exynoautov9: do not define number of clocks in bindings clk: samsung: exynos850: do not define number of clocks in bindings clk: samsung: exynos7885: do not define number of clocks in bindings clk: samsung: exynos5433: do not define number of clocks in bindings clk: samsung: exynos5420: do not define number of clocks in bindings clk: samsung: exynos5410: do not define number of clocks in bindings clk: samsung: exynos5260: do not define number of clocks in bindings clk: samsung: exynos5250: do not define number of clocks in bindings clk: samsung: exynos4: do not define number of clocks in bindings clk: samsung: exynos3250: do not define number of clocks in bindings * clk-annotate: clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by clk: Annotate struct clk_hw_onecell_data with __counted_by * clk-marvell: clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source clk: mmp: Remove old non-OF clock drivers * clk-lmk: clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks
6 parents 032bcf7 + 960535d + e5546e9 + a5be6db + 3b99cd2 + 6aa8dc6 commit 3462100

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‎Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8 Audio Clock Mux
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maintainers:
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- Shengjiu Wang <shengjiu.wang@nxp.com>
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description: |
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NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
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used to control Audio related clock on the SoC.
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properties:
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compatible:
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enum:
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- fsl,imx8dxl-acm
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- fsl,imx8qm-acm
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- fsl,imx8qxp-acm
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reg:
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maxItems: 1
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power-domains:
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minItems: 13
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maxItems: 21
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'#clock-cells':
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const: 1
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description:
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
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for the full list of i.MX8 ACM clock IDs.
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clocks:
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minItems: 13
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maxItems: 27
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clock-names:
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minItems: 13
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maxItems: 27
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required:
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- compatible
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- reg
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- power-domains
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- '#clock-cells'
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qxp-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 18
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maxItems: 18
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_ESAI_1
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SAI_6
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- description: power domain of IMX_SC_R_SAI_7
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_SPDIF_1
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 27
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maxItems: 27
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: mlb_clk
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- const: hdmi_rx_mclk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: esai1_rx_clk
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- const: esai1_rx_hf_clk
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- const: esai1_tx_clk
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- const: esai1_tx_hf_clk
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- const: spdif0_rx
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- const: spdif1_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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- const: sai5_tx_bclk
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- const: sai6_rx_bclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8dxl-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 13
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maxItems: 13
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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additionalProperties: false
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examples:
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# Clock Control Module node:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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clock-controller@59e00000 {
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compatible = "fsl,imx8qxp-acm";
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reg = <0x59e00000 0x1d0000>;
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#clock-cells = <1>;
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power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
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<&pd IMX_SC_R_AUDIO_CLK_1>,
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<&pd IMX_SC_R_MCLK_OUT_0>,
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<&pd IMX_SC_R_MCLK_OUT_1>,
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<&pd IMX_SC_R_AUDIO_PLL_0>,
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<&pd IMX_SC_R_AUDIO_PLL_1>,
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<&pd IMX_SC_R_ASRC_0>,
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<&pd IMX_SC_R_ASRC_1>,
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<&pd IMX_SC_R_ESAI_0>,
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<&pd IMX_SC_R_SAI_0>,
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<&pd IMX_SC_R_SAI_1>,
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<&pd IMX_SC_R_SAI_2>,
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<&pd IMX_SC_R_SAI_3>,
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<&pd IMX_SC_R_SAI_4>,
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<&pd IMX_SC_R_SAI_5>,
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<&pd IMX_SC_R_SPDIF_0>,
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<&pd IMX_SC_R_MQS_0>;
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clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
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<&aud_rec1_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
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<&clk_ext_aud_mclk0>,
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<&clk_ext_aud_mclk1>,
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<&clk_esai0_rx_clk>,
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<&clk_esai0_rx_hf_clk>,
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<&clk_esai0_tx_clk>,
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<&clk_esai0_tx_hf_clk>,
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<&clk_spdif0_rx>,
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<&clk_sai0_rx_bclk>,
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<&clk_sai0_tx_bclk>,
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<&clk_sai1_rx_bclk>,
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<&clk_sai1_tx_bclk>,
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<&clk_sai2_rx_bclk>,
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<&clk_sai3_rx_bclk>,
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<&clk_sai4_rx_bclk>;
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clock-names = "aud_rec_clk0_lpcg_clk",
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"aud_rec_clk1_lpcg_clk",
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"aud_pll_div_clk0_lpcg_clk",
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"aud_pll_div_clk1_lpcg_clk",
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"ext_aud_mclk0",
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"ext_aud_mclk1",
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"esai0_rx_clk",
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"esai0_rx_hf_clk",
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"esai0_tx_clk",
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"esai0_tx_hf_clk",
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"spdif0_rx",
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"sai0_rx_bclk",
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"sai0_tx_bclk",
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"sai1_rx_bclk",
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"sai1_tx_bclk",
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"sai2_rx_bclk",
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"sai3_rx_bclk",
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"sai4_rx_bclk";
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};

‎drivers/clk/clk-aspeed.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -701,6 +701,7 @@ static void __init aspeed_cc_init(struct device_node *np)
701701
GFP_KERNEL);
702702
if (!aspeed_clk_data)
703703
return;
704+
aspeed_clk_data->num = ASPEED_NUM_CLKS;
704705

705706
/*
706707
* This way all clocks fetched before the platform device probes,
@@ -732,8 +733,6 @@ static void __init aspeed_cc_init(struct device_node *np)
732733
aspeed_ast2500_cc(map);
733734
else
734735
pr_err("unknown platform, failed to add clocks\n");
735-
736-
aspeed_clk_data->num = ASPEED_NUM_CLKS;
737736
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
738737
if (ret)
739738
pr_err("failed to add DT provider: %d\n", ret);

‎drivers/clk/clk-ast2600.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -839,6 +839,7 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
839839
ASPEED_G6_NUM_CLKS), GFP_KERNEL);
840840
if (!aspeed_g6_clk_data)
841841
return;
842+
aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
842843

843844
/*
844845
* This way all clocks fetched before the platform device probes,
@@ -860,7 +861,6 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
860861
}
861862

862863
aspeed_g6_cc(map);
863-
aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
864864
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
865865
if (ret)
866866
pr_err("failed to add DT provider: %d\n", ret);

‎drivers/clk/clk-gemini.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -402,6 +402,7 @@ static void __init gemini_cc_init(struct device_node *np)
402402
GFP_KERNEL);
403403
if (!gemini_clk_data)
404404
return;
405+
gemini_clk_data->num = GEMINI_NUM_CLKS;
405406

406407
/*
407408
* This way all clock fetched before the platform device probes,
@@ -455,7 +456,6 @@ static void __init gemini_cc_init(struct device_node *np)
455456
gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
456457

457458
/* Register the clocks to be accessed by the device tree */
458-
gemini_clk_data->num = GEMINI_NUM_CLKS;
459459
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
460460
}
461461
CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);

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