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Merge tag 'clk-imx-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa: - Add the PDM IPC clock for i.MX93 - Add 519.75MHz frequency support for i.MX9 PLL - Simplify the .determine_rate() for GPR mux - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource - Add the audio mux clock to i.MX8 - Fix the SPLL2 MULT range for PLLv4 - Update the SPLL2 type in i.MX8ULP - Fix the SAI4 clock on i.MX8MP - Add silicon revision print for i.MX25 on clocks init - Drop the return value from __mx25_clocks_init - Fix the clock pauses on no-op set_rate for i.MX8M composite clock - Drop restrictions for PLL14xx and fix its max prediv value - Drop the 393216000 and 361267200 from PLL14xx rate table to allow glitch free switching * tag 'clk-imx-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz clk: imx: pll14xx: align pdiv with reference manual clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op clk: imx25: make __mx25_clocks_init return void clk: imx25: print silicon revision during init dt-bindings: clocks: imx8mp: make sai4 a dummy clock clk: imx8mp: fix sai4 clock clk: imx: imx8ulp: update SPLL2 type clk: imx: pllv4: Fix SPLL2 MULT range clk: imx: imx8: add audio clock mux driver dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() clk: imx: clk-gpr-mux: Simplify .determine_rate() clk: imx: Add 519.75MHz frequency support for imx9 pll clk: imx93: Add PDM IPG clk dt-bindings: clock: imx93: Add PDM IPG clk
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‎Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,282 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8 Audio Clock Mux
8+
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maintainers:
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- Shengjiu Wang <shengjiu.wang@nxp.com>
11+
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description: |
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NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
14+
used to control Audio related clock on the SoC.
15+
16+
properties:
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compatible:
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enum:
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- fsl,imx8dxl-acm
20+
- fsl,imx8qm-acm
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- fsl,imx8qxp-acm
22+
23+
reg:
24+
maxItems: 1
25+
26+
power-domains:
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minItems: 13
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maxItems: 21
29+
30+
'#clock-cells':
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const: 1
32+
description:
33+
The clock consumer should specify the desired clock by having the clock
34+
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
35+
for the full list of i.MX8 ACM clock IDs.
36+
37+
clocks:
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minItems: 13
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maxItems: 27
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clock-names:
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minItems: 13
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maxItems: 27
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required:
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- compatible
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- reg
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- power-domains
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- '#clock-cells'
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qxp-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
65+
- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 18
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maxItems: 18
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_ESAI_1
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SAI_6
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- description: power domain of IMX_SC_R_SAI_7
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_SPDIF_1
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 27
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maxItems: 27
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
146+
- const: aud_rec_clk1_lpcg_clk
147+
- const: aud_pll_div_clk0_lpcg_clk
148+
- const: aud_pll_div_clk1_lpcg_clk
149+
- const: mlb_clk
150+
- const: hdmi_rx_mclk
151+
- const: ext_aud_mclk0
152+
- const: ext_aud_mclk1
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- const: esai0_rx_clk
154+
- const: esai0_rx_hf_clk
155+
- const: esai0_tx_clk
156+
- const: esai0_tx_hf_clk
157+
- const: esai1_rx_clk
158+
- const: esai1_rx_hf_clk
159+
- const: esai1_tx_clk
160+
- const: esai1_tx_hf_clk
161+
- const: spdif0_rx
162+
- const: spdif1_rx
163+
- const: sai0_rx_bclk
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- const: sai0_tx_bclk
165+
- const: sai1_rx_bclk
166+
- const: sai1_tx_bclk
167+
- const: sai2_rx_bclk
168+
- const: sai3_rx_bclk
169+
- const: sai4_rx_bclk
170+
- const: sai5_tx_bclk
171+
- const: sai6_rx_bclk
172+
173+
- if:
174+
properties:
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compatible:
176+
contains:
177+
enum:
178+
- fsl,imx8dxl-acm
179+
then:
180+
properties:
181+
power-domains:
182+
items:
183+
- description: power domain of IMX_SC_R_AUDIO_CLK_0
184+
- description: power domain of IMX_SC_R_AUDIO_CLK_1
185+
- description: power domain of IMX_SC_R_MCLK_OUT_0
186+
- description: power domain of IMX_SC_R_MCLK_OUT_1
187+
- description: power domain of IMX_SC_R_AUDIO_PLL_0
188+
- description: power domain of IMX_SC_R_AUDIO_PLL_1
189+
- description: power domain of IMX_SC_R_ASRC_0
190+
- description: power domain of IMX_SC_R_SAI_0
191+
- description: power domain of IMX_SC_R_SAI_1
192+
- description: power domain of IMX_SC_R_SAI_2
193+
- description: power domain of IMX_SC_R_SAI_3
194+
- description: power domain of IMX_SC_R_SPDIF_0
195+
- description: power domain of IMX_SC_R_MQS_0
196+
197+
clocks:
198+
minItems: 13
199+
maxItems: 13
200+
201+
clock-names:
202+
items:
203+
- const: aud_rec_clk0_lpcg_clk
204+
- const: aud_rec_clk1_lpcg_clk
205+
- const: aud_pll_div_clk0_lpcg_clk
206+
- const: aud_pll_div_clk1_lpcg_clk
207+
- const: ext_aud_mclk0
208+
- const: ext_aud_mclk1
209+
- const: spdif0_rx
210+
- const: sai0_rx_bclk
211+
- const: sai0_tx_bclk
212+
- const: sai1_rx_bclk
213+
- const: sai1_tx_bclk
214+
- const: sai2_rx_bclk
215+
- const: sai3_rx_bclk
216+
217+
additionalProperties: false
218+
219+
examples:
220+
# Clock Control Module node:
221+
- |
222+
#include <dt-bindings/clock/imx8-lpcg.h>
223+
#include <dt-bindings/firmware/imx/rsrc.h>
224+
225+
clock-controller@59e00000 {
226+
compatible = "fsl,imx8qxp-acm";
227+
reg = <0x59e00000 0x1d0000>;
228+
#clock-cells = <1>;
229+
power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
230+
<&pd IMX_SC_R_AUDIO_CLK_1>,
231+
<&pd IMX_SC_R_MCLK_OUT_0>,
232+
<&pd IMX_SC_R_MCLK_OUT_1>,
233+
<&pd IMX_SC_R_AUDIO_PLL_0>,
234+
<&pd IMX_SC_R_AUDIO_PLL_1>,
235+
<&pd IMX_SC_R_ASRC_0>,
236+
<&pd IMX_SC_R_ASRC_1>,
237+
<&pd IMX_SC_R_ESAI_0>,
238+
<&pd IMX_SC_R_SAI_0>,
239+
<&pd IMX_SC_R_SAI_1>,
240+
<&pd IMX_SC_R_SAI_2>,
241+
<&pd IMX_SC_R_SAI_3>,
242+
<&pd IMX_SC_R_SAI_4>,
243+
<&pd IMX_SC_R_SAI_5>,
244+
<&pd IMX_SC_R_SPDIF_0>,
245+
<&pd IMX_SC_R_MQS_0>;
246+
clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
247+
<&aud_rec1_lpcg IMX_LPCG_CLK_0>,
248+
<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
249+
<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
250+
<&clk_ext_aud_mclk0>,
251+
<&clk_ext_aud_mclk1>,
252+
<&clk_esai0_rx_clk>,
253+
<&clk_esai0_rx_hf_clk>,
254+
<&clk_esai0_tx_clk>,
255+
<&clk_esai0_tx_hf_clk>,
256+
<&clk_spdif0_rx>,
257+
<&clk_sai0_rx_bclk>,
258+
<&clk_sai0_tx_bclk>,
259+
<&clk_sai1_rx_bclk>,
260+
<&clk_sai1_tx_bclk>,
261+
<&clk_sai2_rx_bclk>,
262+
<&clk_sai3_rx_bclk>,
263+
<&clk_sai4_rx_bclk>;
264+
clock-names = "aud_rec_clk0_lpcg_clk",
265+
"aud_rec_clk1_lpcg_clk",
266+
"aud_pll_div_clk0_lpcg_clk",
267+
"aud_pll_div_clk1_lpcg_clk",
268+
"ext_aud_mclk0",
269+
"ext_aud_mclk1",
270+
"esai0_rx_clk",
271+
"esai0_rx_hf_clk",
272+
"esai0_tx_clk",
273+
"esai0_tx_hf_clk",
274+
"spdif0_rx",
275+
"sai0_rx_bclk",
276+
"sai0_tx_bclk",
277+
"sai1_rx_bclk",
278+
"sai1_tx_bclk",
279+
"sai2_rx_bclk",
280+
"sai3_rx_bclk",
281+
"sai4_rx_bclk";
282+
};

‎drivers/clk/imx/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,11 +32,12 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
3232

3333
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
3434

35-
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
35+
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o
3636
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
3737
clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \
3838
clk-imx8dxl-rsrc.o
3939
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
40+
clk-imx-acm-$(CONFIG_CLK_IMX8QXP) = clk-imx8-acm.o
4041

4142
obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o
4243

‎drivers/clk/imx/clk-composite-8m.c

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
9797
int prediv_value;
9898
int div_value;
9999
int ret;
100-
u32 val;
100+
u32 orig, val;
101101

102102
ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
103103
&prediv_value, &div_value);
@@ -106,13 +106,15 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
106106

107107
spin_lock_irqsave(divider->lock, flags);
108108

109-
val = readl(divider->reg);
110-
val &= ~((clk_div_mask(divider->width) << divider->shift) |
111-
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
109+
orig = readl(divider->reg);
110+
val = orig & ~((clk_div_mask(divider->width) << divider->shift) |
111+
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
112112

113113
val |= (u32)(prediv_value - 1) << divider->shift;
114114
val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
115-
writel(val, divider->reg);
115+
116+
if (val != orig)
117+
writel(val, divider->reg);
116118

117119
spin_unlock_irqrestore(divider->lock, flags);
118120

‎drivers/clk/imx/clk-fracn-gppll.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
8181
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
8282
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
8383
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
84+
PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
8485
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
8586
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
8687
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),

‎drivers/clk/imx/clk-gpr-mux.c

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -65,16 +65,10 @@ static int imx_clk_gpr_mux_set_parent(struct clk_hw *hw, u8 index)
6565
return regmap_update_bits(priv->regmap, priv->reg, priv->mask, val);
6666
}
6767

68-
static int imx_clk_gpr_mux_determine_rate(struct clk_hw *hw,
69-
struct clk_rate_request *req)
70-
{
71-
return clk_mux_determine_rate_flags(hw, req, 0);
72-
}
73-
7468
static const struct clk_ops imx_clk_gpr_mux_ops = {
7569
.get_parent = imx_clk_gpr_mux_get_parent,
7670
.set_parent = imx_clk_gpr_mux_set_parent,
77-
.determine_rate = imx_clk_gpr_mux_determine_rate,
71+
.determine_rate = __clk_mux_determine_rate,
7872
};
7973

8074
struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,

‎drivers/clk/imx/clk-imx25.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include <linux/of.h>
1414
#include <linux/of_address.h>
1515
#include <linux/of_irq.h>
16+
#include <soc/imx/revision.h>
1617

1718
#include "clk.h"
1819

@@ -73,7 +74,7 @@ enum mx25_clks {
7374

7475
static struct clk *clk[clk_max];
7576

76-
static int __init __mx25_clocks_init(void __iomem *ccm_base)
77+
static void __init __mx25_clocks_init(void __iomem *ccm_base)
7778
{
7879
BUG_ON(!ccm_base);
7980

@@ -220,7 +221,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
220221

221222
imx_register_uart_clocks();
222223

223-
return 0;
224+
imx_print_silicon_rev("i.MX25", mx25_revision());
224225
}
225226

226227
static void __init mx25_clocks_init_dt(struct device_node *np)

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