Skip to content

Commit 216be47

Browse files
Shiwu Zhangalexdeucher
authored andcommitted
drm/amdgpu: fix the gb_addr_config_fields init value mismatch
For gfx_v9_4_3 specifically, before regGB_ADDR_CONFIG is overwritten in gfx hw_init it is read out to popluate the gb_addr_config_fields in the sw_init stage, which causes mismatch. Fix it by using the golden value in sw_init as well. v2: This is a driver-set golden reg and keep as it is (Lijo) Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 3bc7bc7 commit 216be47

File tree

1 file changed

+1
-5
lines changed

1 file changed

+1
-5
lines changed

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -916,8 +916,6 @@ static const struct aca_info gfx_v9_4_3_aca_info = {
916916

917917
static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
918918
{
919-
u32 gb_addr_config;
920-
921919
adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
922920
adev->gfx.ras = &gfx_v9_4_3_ras;
923921

@@ -926,9 +924,7 @@ static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
926924
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
927925
adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
928926
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
929-
gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
930-
931-
adev->gfx.config.gb_addr_config = gb_addr_config;
927+
adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG;
932928

933929
adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
934930
REG_GET_FIELD(

0 commit comments

Comments
 (0)