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Merge branches 'clk-socfpga', 'clk-toshiba', 'clk-st' and 'clk-bitmain' into clk-next
 - Clock and reset driver for Toshiba Visconti SoCs * clk-socfpga: clk: socfpga: s10: Make use of the helper function devm_platform_ioremap_resource() clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_resource() clk: socfpga: remove redundant assignment after a mask operation clk: socfpga: remove redundant assignment on division * clk-toshiba: clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC * clk-st: clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent * clk-bitmain: clk: bm1880: remove kfrees on static allocations
5 parents f691c9b + b739bca + 4e31bfa + 5dcc0ef + c861c1b commit 1d0bd12

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‎Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml

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@@ -0,0 +1,57 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings
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maintainers:
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- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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description:
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Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.
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properties:
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compatible:
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const: toshiba,tmpv7708-pipllct
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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description: External reference clock (OSC2)
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maxItems: 1
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required:
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- compatible
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- reg
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- "#clock-cells"
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- clocks
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additionalProperties: false
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examples:
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- |
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osc2_clk: osc2-clk {
41+
compatible = "fixed-clock";
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clock-frequency = <20000000>;
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#clock-cells = <0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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50+
pipllct: clock-controller@24220000 {
51+
compatible = "toshiba,tmpv7708-pipllct";
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reg = <0 0x24220000 0 0x820>;
53+
#clock-cells = <1>;
54+
clocks = <&osc2_clk>;
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};
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};
57+
...

‎Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml

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@@ -0,0 +1,52 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings
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maintainers:
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- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
11+
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description:
13+
Toshia Visconti5 SMU (System Management Unit) which supports the clock
14+
and resets on TMPV770x.
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properties:
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compatible:
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items:
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- const: toshiba,tmpv7708-pismu
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pismu: syscon@24200000 {
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compatible = "toshiba,tmpv7708-pismu", "syscon";
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reg = <0 0x24200000 0 0x2140>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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...

‎MAINTAINERS

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@@ -2782,12 +2782,15 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Supported
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git
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F: Documentation/devicetree/bindings/arm/toshiba.yaml
2785+
F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
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F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
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F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
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F: Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
27872789
F: Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
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F: Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
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F: Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml
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F: arch/arm64/boot/dts/toshiba/
2793+
F: drivers/clk/visconti/
27912794
F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
27922795
F: drivers/gpio/gpio-visconti.c
27932796
F: drivers/pci/controller/dwc/pcie-visconti.c

‎drivers/clk/Kconfig

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -354,16 +354,6 @@ config COMMON_CLK_STM32MP157
354354
help
355355
Support for stm32mp157 SoC family clocks
356356

357-
config COMMON_CLK_STM32MP157_SCMI
358-
bool "stm32mp157 Clock driver with Trusted Firmware"
359-
depends on COMMON_CLK_STM32MP157
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select COMMON_CLK_SCMI
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select ARM_SCMI_PROTOCOL
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default y
363-
help
364-
Support for stm32mp157 SoC family clocks with Trusted Firmware using
365-
SCMI protocol.
366-
367357
config COMMON_CLK_STM32F
368358
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
369359
help
@@ -432,6 +422,7 @@ source "drivers/clk/sunxi-ng/Kconfig"
432422
source "drivers/clk/tegra/Kconfig"
433423
source "drivers/clk/ti/Kconfig"
434424
source "drivers/clk/uniphier/Kconfig"
425+
source "drivers/clk/visconti/Kconfig"
435426
source "drivers/clk/x86/Kconfig"
436427
source "drivers/clk/xilinx/Kconfig"
437428
source "drivers/clk/zynqmp/Kconfig"

‎drivers/clk/Makefile

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@@ -118,6 +118,7 @@ obj-y += ti/
118118
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
119119
obj-$(CONFIG_ARCH_U8500) += ux500/
120120
obj-y += versatile/
121+
obj-$(CONFIG_COMMON_CLK_VISCONTI) += visconti/
121122
ifeq ($(CONFIG_COMMON_CLK), y)
122123
obj-$(CONFIG_X86) += x86/
123124
endif

‎drivers/clk/clk-bm1880.c

Lines changed: 2 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -522,14 +522,6 @@ static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_cl
522522
return hw;
523523
}
524524

525-
static void bm1880_clk_unregister_pll(struct clk_hw *hw)
526-
{
527-
struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw);
528-
529-
clk_hw_unregister(hw);
530-
kfree(pll_hw);
531-
}
532-
533525
static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks,
534526
int num_clks,
535527
struct bm1880_clock_data *data)
@@ -555,7 +547,7 @@ static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks,
555547

556548
err_clk:
557549
while (i--)
558-
bm1880_clk_unregister_pll(data->hw_data.hws[clks[i].pll.id]);
550+
clk_hw_unregister(data->hw_data.hws[clks[i].pll.id]);
559551

560552
return PTR_ERR(hw);
561553
}
@@ -695,14 +687,6 @@ static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_cl
695687
return hw;
696688
}
697689

698-
static void bm1880_clk_unregister_div(struct clk_hw *hw)
699-
{
700-
struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
701-
702-
clk_hw_unregister(hw);
703-
kfree(div_hw);
704-
}
705-
706690
static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks,
707691
int num_clks,
708692
struct bm1880_clock_data *data)
@@ -729,7 +713,7 @@ static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks,
729713

730714
err_clk:
731715
while (i--)
732-
bm1880_clk_unregister_div(data->hw_data.hws[clks[i].div.id]);
716+
clk_hw_unregister(data->hw_data.hws[clks[i].div.id]);
733717

734718
return PTR_ERR(hw);
735719
}

‎drivers/clk/socfpga/clk-agilex.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -500,12 +500,10 @@ static int n5x_clkmgr_init(struct platform_device *pdev)
500500
struct device_node *np = pdev->dev.of_node;
501501
struct device *dev = &pdev->dev;
502502
struct stratix10_clock_data *clk_data;
503-
struct resource *res;
504503
void __iomem *base;
505504
int i, num_clks;
506505

507-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
508-
base = devm_ioremap_resource(dev, res);
506+
base = devm_platform_ioremap_resource(pdev, 0);
509507
if (IS_ERR(base))
510508
return PTR_ERR(base);
511509

‎drivers/clk/socfpga/clk-gate.c

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Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
3434

3535
if (streq(name, SOCFPGA_L4_MP_CLK)) {
3636
l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
37-
return l4_src &= 0x1;
37+
return l4_src & 0x1;
3838
}
3939
if (streq(name, SOCFPGA_L4_SP_CLK)) {
4040
l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
@@ -43,7 +43,7 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
4343

4444
perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
4545
if (streq(name, SOCFPGA_MMC_CLK))
46-
return perpll_src &= 0x3;
46+
return perpll_src & 0x3;
4747
if (streq(name, SOCFPGA_NAND_CLK) ||
4848
streq(name, SOCFPGA_NAND_X_CLK))
4949
return (perpll_src >> 2) & 3;

‎drivers/clk/socfpga/clk-pll-s10.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
113113
SWCTRLBTCLKSEL_MASK) >>
114114
SWCTRLBTCLKSEL_SHIFT);
115115
div += 1;
116-
return parent_rate /= div;
116+
return parent_rate / div;
117117
}
118118

119119

‎drivers/clk/socfpga/clk-s10.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -388,12 +388,10 @@ static int s10_clkmgr_init(struct platform_device *pdev)
388388
struct device_node *np = pdev->dev.of_node;
389389
struct device *dev = &pdev->dev;
390390
struct stratix10_clock_data *clk_data;
391-
struct resource *res;
392391
void __iomem *base;
393392
int i, num_clks;
394393

395-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
396-
base = devm_ioremap_resource(dev, res);
394+
base = devm_platform_ioremap_resource(pdev, 0);
397395
if (IS_ERR(base)) {
398396
pr_err("%s: failed to map clock registers\n", __func__);
399397
return PTR_ERR(base);

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